|
|
All Technical Committee Conferences (Searched in: All Years)
|
|
Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
|
Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD |
2008-12-12 16:35 |
Tokyo |
Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan |
Post-Silicon Programmed Body-Biasing Platform Suppressing Device Variability in 45 nm CMOS Technology Issei Kashima, Hiroaki Suzuki, Masanori Kurimoto (Renesas Technology Corp), Tadao Yamanaka (Renesas Design), Hidehiro Takata (Renesas Technology Corp), Hiroshi Makino (Osaka Institute of Tech), Hirofumi Shinohara (Renesas Technology Corp) ICD2008-128 |
The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technolog... [more] |
ICD2008-128 pp.137-142 |
VLD |
2008-09-29 13:30 |
Ishikawa |
|
[Invited Talk]
Phase-Adjustable Error Detection Flip-Flops with 2-Stage Hold Driven Optimization and Slack Based Grouping Scheme for Dynamic Voltage Scaling Masanori Kurimoto, Hiroaki Suzuki (Renesas Technology), Rei Akiyama, Tadao Yamanaka, Haruyuki Okuma (Renesas Design), Hidehiro Takata, Hirofumi Shinohara (Renesas Technology) VLD2008-47 |
[more] |
VLD2008-47 pp.1-6 |
|
|
|
Copyright and reproduction :
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
|
[Return to Top Page]
[Return to IEICE Web Page]
|