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 Results 61 - 64 of 64 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
CAS, SIP, VLD 2005-06-28
14:15
Miyagi Tohoku University A Memory-Reduction Method for Partially-Parallel LDPC Decoder Based on Min-Sum Algorithm
Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.)
In this paper, we propose a memory-reduction method for partially-parallel LDPC decoder based on min-sum algorithm. We ... [more] CAS2005-22 VLD2005-33 SIP2005-46
pp.43-48
IT 2005-05-25
13:30
Overseas Univ. of Hawaii Comparison of Rate Estimation Techniques for Rate-Compatible LDPC Codes
Tomoyasu Yoshikawa, Tetsuo Tsujioka, Hisayoshi Sugiyama (Osaka City Univ.), Masashi Murata (Ryukoku Univ.)
Recently, Rate-Compatible LDPC (RC-LDPC) codes have become attractive research topics on channel coding. RC-LDPC codes p... [more] IT2005-4
pp.18-23
IT, WBS, ISEC 2005-03-17
13:00
Kyoto Kyoto Univ. Design of LDPC codes using degree distributions of Tanner graphs
Shinya Miyamoto, Kenta Kasai, Kohichi Sakaniwa (Tokyo Tech)
Decoding performance of LDPC(Low-Density Parity-Check) codes over a binary erasure channel(BEC) is highly dependent on t... [more] IT2004-60 ISEC2004-116 WBS2004-175
pp.61-66
CS, CAS, SIP 2005-03-15
10:45
Okayama Okayama Prefectural University A Study on Rate Estimation Technique of Rate-Compatible LDPC Codes
Tomoyasu Yoshikawa, Tetsuo Tsujioka, Hisayoshi Sugiyama, Masashi Murata (Osaka City Univ.)
Recently, Rate-Compatible LDPC (RC-LDPC) codes are attractive research topics on channel coding. RC-LDPC codes provide v... [more] CAS2004-100 SIP2004-143 CS2004-236
pp.19-24
 Results 61 - 64 of 64 [Previous]  /   
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