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All Technical Committee Conferences (Searched in: All Years)
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| Search Results: Conference Papers |
| Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail] |
2007-11-22
13:50 |
Fukuoka |
Kitakyushu International Conference Center |
Parallel prefix adder synthesis based on Ling’s carry computation
Taeko Matsunaga, Shinji Kimura (Waseda Univ.), Yusuke Matsunaga (Kyushu Univ.) |
Ling adders calculate carry propagation based on adjacent bit pairs,
and can be formulated as parallel prefix adders. I... [more] |
VLD2007-97 DC2007-52
pp.49-54 |
| VLD, IPSJ-SLDM |
2007-05-11
11:45 |
Kyoto |
Kyodai Kaikan |
On power-conscious approach for prefix graph synthesis
Taeko Matsunaga (Waseda Univ), Yusuke Matsunaga (Kyushu Univ.) |
A prefix graph visualizes a global structure of a parallel prefix
adder at technology independent level. Several approa... [more] |
VLD2007-12
pp.31-36 |
| ICD, VLD |
2007-03-08
15:30 |
Okinawa |
Mielparque Okinawa |
Design Method of Radix Converters Using Arithmetic Decompositions (3)
Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT), Toshikazu Aoyama (Meiji Univ.) |
In digital signal processing, radixes other than two are often used
for high-speed computation.
In the computation f... [more] |
VLD2006-135 ICD2006-226
pp.97-102 |
| ICD, SIP, IE, IPSJ-SLDM |
2006-10-27
09:20 |
Miyagi |
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On synthesis algorithm for parallel prefix adders using dynamic programming
Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.) |
This paper addresses parallel prefix adder synthesis which targets area minimization under given timing constraints. Th... [more] |
SIP2006-102 ICD2006-128 IE2006-80
pp.7-12 |
| VLD, ICD, DC, IPSJ-SLDM |
2005-12-01
14:20 |
Fukuoka |
Kitakyushu International Conference Center |
Consideration on Delay Estimation Methods for Prefix Graphs
Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.) |
Prefix graph is an abstract representation of a parallel prefix adder and used to compare characteristics of various typ... [more] |
VLD2005-69 ICD2005-164 DC2005-46
pp.49-54 |
| MSS, CAS |
2004-11-04
11:20 |
Aichi |
Aichi Pref. Univ. |
Arithmetic Cost Reduction Algorithm for Linear Transformation Circuits Considering the Synthesis Order of Coeficient Set
Keisuke Sato, Takao Sasaki, Hisamichi Toyoshima (Kanagawa Univ.) |
For synthesis of linear transformation circuits, it is generally used that the coefficient matrix is partitioned
i... [more] |
CAS2004-46 CST2004-25
pp.25-28 |
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