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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] 2016-01-21
13:25		 Kanagawa Hiyoshi Campus, Keio University A floorplan-driven high-level synthesis algorithm resilient to dynamic delay variations
Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-105 CPSY2015-137 RECONF2015-87		 Recently, we have proposed a multi-scenario high-level synthesis algorithm targeting static process variations. The algo... [more] VLD2015-105 CPSY2015-137 RECONF2015-87
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