| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SCE | 2020-01-17 13:15 |
Kanagawa | [Poster Presentation]
A Routing Method with Wire Length Matching for RSFQ Logic Circuits Using Thin PTLs Kei Kitamura (Kyoto Univ), Kazuyoshi Takagi (Mie Univ), Naofumi Takagi (Kyoto Univ)  SCE2019-35 |
A routing method with wire length matching using thin PTLs for RSFQ circuits is proposed. For AIST-ADP2 fabrication tech... [more] | SCE2019-35 pp.23-25 |
|
| VLD | 2015-03-03 15:25 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
A Length Matching Routing Method for Disordered Pins in PCB Design Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe (Waseda Univ.) VLD2014-171 |
In this paper, for the disordered pins in printed circuit board (PCB) design, a heuristics algorithm is proposed to obta... [more] | VLD2014-171 pp.103-108 |
| VLD | 2013-03-05 14:30 |
Okinawa | Okinawa Seinen Kaikan | A Routing Method Considering Wirelength of Each Net for Single Layer PCB Routing Kyosuke Shinoda, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2012-149 |
In recent Printed Circuit Board (PCB) design, due to the growth of the density and the increase of the design scale the ... [more] | VLD2012-149 pp.77-82 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 17:25 |
Kanagawa | An Improved Routing Method using Minimum Cost Flow for Routes with Target Wire Lengths Kazuo Yamane, Kunihiro Fujiyoshi (TUAT) VLD2012-121 CPSY2012-70 RECONF2012-75 |
Due to the increase of operation frequency, influence of routing delays is increasing. So it is important to obtain the ... [more] | VLD2012-121 CPSY2012-70 RECONF2012-75 pp.81-86 |
|
| VLD | 2012-03-06 16:20 |
Oita | B-con Plaza | A Length Matching Routing Algorithm on Single Layer Using Longer Path Algorithm for Single Net Syouhei Furuyama, Yukihide Kohira (UoA) VLD2011-131 |
Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve spec... [more] | VLD2011-131 pp.67-72 |
| VLD | 2010-09-27 17:00 |
Kyoto | Kyoto Institute of Technology | [Invited Talk]
Length Matching Routing on Single Layer for PCB Routing Design Yukihide Kohira (UoA), Atsushi Takahashi (Osaka Univ.) VLD2010-47 |
Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve spec... [more] | VLD2010-47 pp.31-36 |
| VLD | 2009-09-24 14:20 |
Osaka | Osaka University | A Wall Generation for Trunk Routing of Multiple Nets on Single Layer Yukihide Kohira (Univ. of Aizu.), Atsushi Takahashi (Osaka Univ.) VLD2009-31 |
In this paper, we propose a wall generation for trunk routing of multiple nets on single layer. An existing routing meth... [more] | VLD2009-31 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 14:55 |
Fukuoka | Kitakyushu Science and Research Park | CAFE router: A Fast Connectivity Aware Multi-net Routing Algorithm for Routing Grid with Obstacles Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) VLD2008-72 DC2008-40 |
Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve spec... [more] | VLD2008-72 DC2008-40 pp.73-78 |
[Return to Top Page]