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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD |
2016-03-01 15:10 |
Okinawa |
Okinawa Seinen Kaikan |
FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127 |
Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] |
VLD2015-127 pp.93-98 |
ITS, IE, ITE-AIT, ITE-HI, ITE-ME, ITE-MMS, ITE-CE [detail] |
2016-02-22 11:45 |
Hokkaido |
Hokkaido Univ. |
[Encouragement Talk]
Development of Pulse Sensor Embedded Video Game Controller Erika Abe (Kyoto Univ.), Hiroshi Chigira (NTT), Koichi Fujiwara, Manabu Kano (Kyoto Univ.), Toshitaka Yamakawa (Kumamoto Univ.) |
[more] |
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VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:35 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50 |
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] |
VLD2015-54 DC2015-50 pp.99-104 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita |
B-ConPlaza |
A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-85 DC2014-39 |
Recently, high-level synthesis (HLS) techniques for FPGA designs are required such as in image pro- cessing and computer... [more] |
VLD2014-85 DC2014-39 pp.99-104 |
CAS, SIP, MSS, VLD, SIS [detail] |
2014-07-11 14:00 |
Hokkaido |
Hokkaido University |
A floorplan-driven high-level synthesis algorithm for reducing multiplexer inputs targeting FPGAs Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) CAS2014-41 VLD2014-50 SIP2014-62 MSS2014-41 SIS2014-41 |
[more] |
CAS2014-41 VLD2014-50 SIP2014-62 MSS2014-41 SIS2014-41 pp.219-224 |
IBISML |
2012-11-08 15:00 |
Tokyo |
Bunkyo School Building, Tokyo Campus, Tsukuba Univ. |
An Efficient Input Variable Selection for a Linear Regression Model by NC Spectral Clustering Koichi Fujiwara (Kyoto Univ.), Hiroshi Sawada (NTT), Manabu Kano (Kyoto Univ.) IBISML2012-84 |
Linear regression models have been widely accepted in many scientific and engineering fields for the estimation or inter... [more] |
IBISML2012-84 pp.359-366 |
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