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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2011-03-04
14:00		 Okinawa Okinawaken-Danjo-Kyodo-Sankaku Center Acceleration of Bounded Model Checking for Sequential Circuits with Two-phase Verification
Norihiro Ono, Kazuhiro Nakamura, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) VLD2010-143		  [more] VLD2010-143
pp.159-164
VLD 2010-03-12
13:30		 Okinawa   Circuit conversion for reducing false negatives on formal verification of sequential circuit
Norihiro Ono, Kazuhiro Nakamura, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) VLD2009-125		 This paper proposes a reducing method of false negatives by the circuit conversion. We focus that the false negatives oc... [more] VLD2009-125
pp.157-162
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