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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2015-12-03
10:50		 Nagasaki Nagasaki Kinro Fukushi Kaikan On Correction of Temperature Influence to Delay Measurement in FPGAs
Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) VLD2015-63 DC2015-59		 As a means for delay testing for VLSIs in field, a measurement method of a path delay for a logic circuit using variable... [more] VLD2015-63 DC2015-59
pp.165-170
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-29
09:20		 Kagoshima   Design and evaluation of circuits to control scan-in power in logic BIST
Takaaki Kato, Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) VLD2013-93 DC2013-59		 Power reduction during Logic BIST is a crucial problem; however, power controlling technologies are required as well as ... [more] VLD2013-93 DC2013-59
pp.233-238
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