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Paper Abstract and Keywords
Presentation 2013-11-29 09:20
Design and evaluation of circuits to control scan-in power in logic BIST
Takaaki Kato, Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) VLD2013-93 DC2013-59
Abstract (in Japanese) (See Japanese page) 
(in English) Power reduction during Logic BIST is a crucial problem; however, power controlling technologies are required as well as power reduction techniques because the required power level differs depending on its applications. The authors’ previous study has proposed a power reducing circuit that controls toggle rate during scan-in mode. This paper proposes a power controlling method, which is based on the power controlling circuit, and its effectiveness is evaluated by measurement of a TEG that equips the power controlling circuit.
Keyword (in Japanese) (See Japanese page) 
(in English) BIST / scan test / low power dissipation / scan-in power / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 321, DC2013-59, pp. 233-238, Nov. 2013.
Paper # DC2013-59 
Date of Issue 2013-11-20 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-93 DC2013-59

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design and evaluation of circuits to control scan-in power in logic BIST 
Sub Title (in English)  
Keyword(1) BIST  
Keyword(2) scan test  
Keyword(3) low power dissipation  
Keyword(4) scan-in power  
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Keyword(6)  
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1st Author's Name Takaaki Kato  
1st Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
2nd Author's Name Takeru Kina  
2nd Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
3rd Author's Name Yousuke Miyake  
3rd Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
4th Author's Name Yasuo Sato  
4th Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
5th Author's Name Seiji Kajihara  
5th Author's Affiliation Kyushu Institute of Technology (Kyushu Inst. of Tech.)
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Speaker Author-1 
Date Time 2013-11-29 09:20:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2013-93, DC2013-59 
Volume (vol) vol.113 
Number (no) no.320(VLD), no.321(DC) 
Page pp.233-238 
#Pages 6 
Date of Issue 2013-11-20 (VLD, DC) 

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