| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ISEC | 2009-05-22 11:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Generalized Zero-offset Power Analyses for Restricted Masking Scheme Yuichi Komano, Hideo Shimizu, Hanae Nozaki, Atsushi Shimbo (Toshiba Corp.)  ISEC2009-4 |
[more] | ISEC2009-4 pp.21-28 |
| WBS, IT, ISEC | 2009-03-10 16:05 |
Hokkaido | Hakodate Mirai Univ. | On the Security of Torus-based Cryptography and Pairing Inversion Problem Hirofumi Muratani, Tomoko Yonemura, Kenji Ohkuma, Taichi Isogai, Kenichiro Furuta, Yoshikazu Hanatani, Yuichi Komano, Hanae Nozaki, Atsushi Shimbo (Toshiba Corp.) IT2008-128 ISEC2008-186 WBS2008-141 |
[more] | IT2008-128 ISEC2008-186 WBS2008-141 pp.551-556 |
| ISEC | 2008-12-17 14:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Cryptosystems on Algebraic Tori
-- Some Efficient Algorithms for Squaring -- Tomoko Yonemura, Kenichiro Furuta, Yoshikazu Hanatani, Taichi Isogai, Yuichi Komano, Hirofumi Muratani, Hanae Nozaki, Kenji Ohkuma, Atsushi Shimbo (Toshiba Corp.) ISEC2008-97 |
To construct a efficient algebraic torus-based public key encryption scheme is one of our goals. An efficient scheme is ... [more] | ISEC2008-97 pp.45-52 |
| ISEC | 2008-12-17 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Fast Exponentiation Methods for Cryptosystems on Algebraic Tori Taichi Isogai, Kenji Ohkuma, Yuichi Komano, Atsushi Shimbo, Hanae Nozaki, Yoshikazu Hanatani, Kenichiro Furuta, Hirofumi Muratani, Tomoko Yonemura (Toshiba) ISEC2008-98 |
[more] | ISEC2008-98 pp.53-60 |
| ISEC, LOIS | 2008-11-13 15:15 |
Aichi | Nagoya Noh Theater | On the Hardness of Discrete Logarithm Problem in Algebraic Tori Hirofumi Muratani, Tomoko Yonemura, Taichi Isogai, Kenji Ohkuma, Yoshikazu Hanatani, Kenichiro Furuta, Yuichi Komano, Hanae Nozaki, Atsushi Shimbo (Toshiba Corporation) ISEC2008-78 OIS2008-54 |
[more] | ISEC2008-78 OIS2008-54 pp.35-40 |
| ISEC | 2008-09-12 14:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Cryptosystems on Algebraic Tori
-- Parameter Generation with Security and Efficiency -- Tomoko Yonemura, Kenichiro Furuta, Yoshikazu Hanatani, Taichi Isogai, Yuichi Komano, Hirofumi Muratani, Hanae Nozaki, Kenji Ohkuma, Atsushi Shimbo (TOSHIBA Corp.) ISEC2008-67 |
We study on algebraic tori defined on extension field as cryptographic groups to construct public key encryption schemes... [more] | ISEC2008-67 pp.25-32 |
| ISEC | 2008-05-16 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Reconsideration of Algorithmic Tamper Proof Devices using PIN (part 2) Yuichi Komano (Toshiba), Kazuo Ohta (UEC), Hideyuki Miyake, Atsushi Shimbo (Toshiba) ISEC2008-7 |
Gennaro et al.~discussed the algorithmic tamper proof (ATP) devices using the personal identification number (PIN); and ... [more] | ISEC2008-7 pp.43-48 |
| ISEC | 2005-09-16 10:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Influence of Random Numbers in a DPA Data Masking Countermeasure Hanae Nozaki, Shinichi Yasuda, Koichi Fujisaki, Atsushi Shimbo, Shinobu Fujita (Toshiba) |
In general DPA countermeasures, random numbers used as data masks have an important role to realize DPA resistance. To ... [more] |
ISEC2005-77 pp.7-13 |
| ISEC, IPSJ-CSEC, SITE | 2005-07-21 11:35 |
Iwate | Iwate Prefectural University | Development of DPA evaluation platform for 32 bit processor Koichi Fujisaki, Hideo Shimizu, Atsushi Shimbo (Toshiba Corp.) |
[more] | ISEC2005-19 SITE2005-17 pp.75-82 |
| ISEC | 2005-05-18 13:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Ring Signature Schemes with Innocence Assertion Revisited (Part 2)
-- Group Signatures Strengthening the Signers' Privacy -- Yuichi Komano (Toshiba), Kazuo Ohta (UEC), Atsushi Shimbo, Shinichi Kawamura (Toshiba) |
This paper reconsiders the ring signature scheme with innocence assertion [10] as a group signature scheme. The ring sig... [more] | ISEC2005-2 pp.9-16 |
| ISEC, IPSJ-CSEC | 2004-07-21 09:40 |
Tokushima | Tokushima Univ. | Development of DPA evaluation platform for 8 bit processor Koichi Fujisaki, Yuki Tomoeda, Hideyuki Miyake, Yuichi Komano, Atsushi Shimbo, Shinichi Kawamura (Toshiba) |
[more] | ISEC2004-55 pp.95-102 |
[Return to Top Page]