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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2023-11-17
14:50
Kumamoto Civic Auditorium Sears Home Yume Hall
(Primary: On-site, Secondary: Online)
An Improved Routing Method by SAT for Set-Pair Routing Problem
Koki Nagakura, Kunihiro Fujiyoshi (TUAT) VLD2023-77 ICD2023-85 DC2023-84 RECONF2023-80
A set-pair routing problem is a single-layer routing problem in which combinations of these pins to be connected by rout... [more] VLD2023-77 ICD2023-85 DC2023-84 RECONF2023-80
pp.243-248
VLD 2015-03-03
15:25
Okinawa Okinawa Seinen Kaikan [Memorial Lecture] A Length Matching Routing Method for Disordered Pins in PCB Design
Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe (Waseda Univ.) VLD2014-171
In this paper, for the disordered pins in printed circuit board (PCB) design, a heuristics algorithm is proposed to obta... [more] VLD2014-171
pp.103-108
VLD, IPSJ-SLDM 2013-05-16
09:50
Fukuoka Kitakyushu International Conference Center A Longest Path Algorithm for Differential Pair Net Considering Connectivity
Koji Yamazaki, Yukihide Kohira (Univ. of Aizu) VLD2013-3
In recent years, due to the speedup and miniaturization in LSI systems, PCB routing design uses many differential pair n... [more] VLD2013-3
pp.13-18
CPSY, VLD, RECONF, IPSJ-SLDM [detail] 2013-01-16
17:25
Kanagawa   An Improved Routing Method using Minimum Cost Flow for Routes with Target Wire Lengths
Kazuo Yamane, Kunihiro Fujiyoshi (TUAT) VLD2012-121 CPSY2012-70 RECONF2012-75
Due to the increase of operation frequency, influence of routing delays is increasing. So it is important to obtain the ... [more] VLD2012-121 CPSY2012-70 RECONF2012-75
pp.81-86
VLD 2012-03-06
16:20
Oita B-con Plaza A Length Matching Routing Algorithm on Single Layer Using Longer Path Algorithm for Single Net
Syouhei Furuyama, Yukihide Kohira (UoA) VLD2011-131
Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve spec... [more] VLD2011-131
pp.67-72
VLD 2010-09-27
17:00
Kyoto Kyoto Institute of Technology [Invited Talk] Length Matching Routing on Single Layer for PCB Routing Design
Yukihide Kohira (UoA), Atsushi Takahashi (Osaka Univ.) VLD2010-47
Due to the increase of operation frequency in recent LSI systems, signal propagation delays are required to achieve spec... [more] VLD2010-47
pp.31-36
VLD 2009-03-11
16:40
Okinawa   A Maximization Method of Parallel Wire Lengths in Routing Area With Lengths in Routing Area with Obstacles
Suguru Suehiro, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.) VLD2008-136
Due to the speeding up of VLSI systems, the PCB routing design is requested to take signal delay and signal integrity in... [more] VLD2008-136
pp.59-64
CAS 2008-02-01
10:30
Okinawa   A note of an estimation of the maximum wire length in the area with obstacle
Suguru Suehiro, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) CAS2007-97
According to the speeding up of VLSI, the requirement to signal is becoming tighter in order to prevent timing errors. T... [more] CAS2007-97
pp.19-23
PN 2007-08-10
13:35
Toyama Kureha-Haitsu, Toyama Proposal of an Alternative Routing in the G-WAPS Core Network
Ayako Kise, Hironari Matsuda, Takayuki Nakata, Tadahiko Yasui (Toyama Pref Univ.) PN2007-18
G-WAPS(WAPS with GMPLS architecture)can't provide a communication path, if there is no idle wavelength in the optimal en... [more] PN2007-18
pp.49-54
 Results 1 - 9 of 9  /   
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