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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2015-03-03
15:50		 Okinawa Okinawa Seinen Kaikan [Memorial Lecture] Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) VLD2014-172		 Near-threshold computing has emerged as a promising solution for drastically improving the energy efficiency of micropro... [more] VLD2014-172
pp.109-114
ICD, VLD 2007-03-09
16:20		 Okinawa Mielparque Okinawa Statistical Delay Computation of Path-Based Timing Analysis Considering Inter and Intra-Chip Variations
Katsumi Homma, Izumi Nitta, Toshiyuki Shibuya (Fujitsu Labs.) 		Statistical Timing Analysis(SSTA) is a method that calculates circuit delay statistically with process variations. In SS... [more] VLD2006-156 ICD2006-247
pp.93-98
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