Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD, IE, SIP, IPSJ-SLDM [detail] |
2011-10-25 13:30 |
Miyagi |
Ichinobo(Sendai) |
FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-73 ICD2011-76 IE2011-72 |
Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions since they can achieve energy-... [more] |
SIP2011-73 ICD2011-76 IE2011-72 pp.73-76 |
RECONF, VLD, CPSY, IPSJ-SLDM [detail] |
2011-01-18 10:55 |
Kanagawa |
Keio Univ (Hiyoshi Campus) |
Feasibility of JHDL for Dynamically Reconfigurable Hardware Design Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) VLD2010-103 CPSY2010-58 RECONF2010-72 |
To develop applications for dynamically reconfigurable hardware, the description language which increases the efficienc... [more] |
VLD2010-103 CPSY2010-58 RECONF2010-72 pp.133-138 |
RECONF |
2010-09-17 11:00 |
Shizuoka |
Shizuoka University (Faculty of Eng., Hall 2) |
Removing context memory from Multi-context Dynamically Reconfigurable Processors Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki (Keio Univ.) RECONF2010-34 |
Although context memory or configuration cache is a key mechanism for quick dyna
mic
reconfiguration of multi-context ... [more] |
RECONF2010-34 pp.97-102 |
VLD, CPSY, RECONF, IPSJ-SLDM |
2009-01-29 08:40 |
Kanagawa |
|
Implementation of Dynamically Reconfigurable Processor MuCCRA-3 and Methods for Reconfiguration Overhead Reduction Toru Sano, Hideharu Amano (Keio Univ) VLD2008-91 CPSY2008-53 RECONF2008-55 |
We have developed and evaluated MuCCRA-1 and 2 in order to analyze
architectural trade-off in dynamically reconfigurab... [more] |
VLD2008-91 CPSY2008-53 RECONF2008-55 pp.1-6 |
RECONF |
2008-09-25 13:30 |
Okayama |
Okayama Univ. |
Implementation of JPEG Encoder on Dynamically Reconfigurable Processor and its Evaluation Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) RECONF2008-24 |
Recently, dynamically reconfigurable hardware has been attracted, the research becomes active, and quantitative evaluati... [more] |
RECONF2008-24 pp.7-12 |
RECONF |
2008-09-26 11:00 |
Okayama |
Okayama Univ. |
Practice Evaluation Dynamically Reconfigurable Processor MuCCRA-2β Yoshiki Saito, Masaru Kato, Shotaro Saito, Toru Sano, Keiichiro Hirai, Takashi Nishimura, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ.) RECONF2008-34 |
Dynamically Reconfigurable Processing Array (DRPA) have been received an attention as a flexible and efficient off-loadi... [more] |
RECONF2008-34 pp.69-74 |
RECONF, CPSY, VLD, IPSJ-SLDM |
2008-01-17 11:05 |
Kanagawa |
Hiyoshi Campus, Keio University |
Implementation of 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication Shotaro Saito, Yasufumi Sugimori, Yoshinori Kohama, Tadahiro Kuroda, Yohei Hasegawa, Hideharu Amano (Keio Univ.) VLD2007-123 CPSY2007-66 RECONF2007-69 |
This paper describes the physical design and evaluation of 3-D dynamically reconfigurable processor MuCCRA-Cube which co... [more] |
VLD2007-123 CPSY2007-66 RECONF2007-69 pp.31-36 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 16:10 |
Fukuoka |
Kitakyushu International Conference Center |
Power analysis on Dynamic Reconfigurable Processor Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.) RECONF2007-41 |
Dynamically Reconfigurable Processors have been expected to improve area and power eciency with the time-multiplexed ex... [more] |
RECONF2007-41 pp.31-36 |
RECONF |
2007-05-18 09:00 |
Ishikawa |
Kanazawa Bunka Hall |
Techniques to decrease the Configuration Data Transfer Time in Dynamically Reconfigurable Processor MuCCRA Toru Sano, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ) RECONF2007-10 |
MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project aims
to establish architectural techniques to devel... [more] |
RECONF2007-10 pp.55-60 |
CPSY, DC |
2006-04-14 10:40 |
Tokyo |
Takeda Hall |
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices Kentaroh Katoh, Yumin Yao, Kazuteru Namba, Hideo Ito (チバダイ) |
This paper proposes a BIST (Built-In Self Test) method for testing the PEs (Processing Elements) of multi-context based ... [more] |
CPSY2006-4 DC2006-4 pp.19-24 |
RECONF |
2005-12-02 09:30 |
Fukuoka |
Kitakyushu International Conference Center |
Development of a Reconfiguration Management Mechanism for Dynamically Reconfigurable System Takanori Susaki, Isao Sakamoto, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
We have developed a dynamically reconfigurable system, which uses an embedded processor FPGA. In this system, an embedde... [more] |
RECONF2005-72 pp.1-6 |
RECONF |
2005-09-15 15:00 |
Hiroshima |
|
Development of a partial reconfiguration controller for an embedded processor FPGA Isao Sakamoto, Takanori Susaki, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
We develop dynamically reconfigurable system,named EXPRESS-2,using partially reconfigurable FPGA. The FPGA contains one ... [more] |
RECONF2005-37 pp.43-48 |