|
|
| Chair |
|
Toshinori Sueyoshi |
| Vice Chair |
|
Akira Nagoya, Tomomi Sato |
| Secretary |
|
Tetsuo Hironaka, Yuichiro Shibata |
| Assistant |
|
Masahiro Iida |
|
| Conference Date |
Thu, Sep 15, 2005 10:30 - 17:15
Fri, Sep 16, 2005 09:00 - 16:00 |
| Topics |
Reconfigurable Systems, etc. |
| Conference Place |
|
Contact
Person |
Associate Prof. Tetsuo Hironaka, Hiroshima City Univ.
0829-44-0430 |
Thu, Sep 15 AM
10:30 - 12:00 |
| (1) |
10:30-11:00 |
Place and Route Processing in Back End Compiler for Reconfigurable Architecture 'PARS' |
Ryuji Hada, Takeshi Fukuda, Kazuya Tanigawa, Akira Kojima, Tetsuo Hironaka (HCU) |
| (2) |
11:00-11:30 |
OS Function and Programing Model for Reconfigurable Architecture |
Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ.) |
| (3) |
11:30-12:00 |
PELOC:An Automatic Place-and-Route Tool for Dynamically Reconfigurable FPGAs
-- Application to the Flexible Processor -- |
Naoto Miyamoto, Takeshi Ohkawa, Amir Jamak, Khan Ashfaquzzaman, Daisuke Iwama, Hiroaki Kanto, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi (Tohoku Univ.) |
| |
12:00-13:00 |
Lunch Break ( 60 min. ) |
Thu, Sep 15 PM
13:00 - 15:30 |
| (4) |
13:00-13:30 |
On LUT cascade realizations of FIR filters using arithmetic decomposition |
Tsutomu Sasao (Kyutech), Yukihiro Iguchi, Takahiro Suzuki (Meiji Univ.) |
| (5) |
13:30-14:00 |
RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices |
Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano (Keio Univ.) |
| (6) |
14:00-14:30 |
Performance and Power Analysis of Time-multiplexed Execution on Dynamically Reconfigurable Processor |
Yohei Hasegawa, Hideharu Amano, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan (Keio Univ.) |
| (7) |
14:30-15:00 |
A Simulation Platform for Designing Self-Reconfigurable Architecture and its application for Study on Coarse-Grained Devices |
Shin'ichi Kouyama, Futoshi Morie, Kentaro Nakahara (Kyoto Univ.), Tomonori Izumi (Ritsumeikan Univ.), Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.) |
| (8) |
15:00-15:30 |
Development of a partial reconfiguration controller for an embedded processor FPGA |
Isao Sakamoto, Takanori Susaki, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
| |
15:30-15:45 |
Break ( 15 min. ) |
Thu, Sep 15 PM
15:45 - 17:15 |
| (9) |
15:45-16:15 |
Feasibility study on a run-time reconfigurable MPEG-2 decoder using functional separation |
Takeru Kisanuki, Isao Sakamoto, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
| (10) |
16:15-16:45 |
Control Mechanism of the FPGA-Based Biochemical Simulator ReCSiP |
Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Toshinori Kojima, Yuri Nishikawa (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) |
| (11) |
16:45-17:15 |
Building of the SBML System for an FPGA-based Biochemical Simulator |
Yow Iwaoka, Yasunori Osana, Masato Yoshimi, Toshinori Kojima, Yuri Nishikawa (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) |
Fri, Sep 16 AM
09:00 - 10:30 |
| (12) |
09:00-09:30 |
Programmable Numerical Function Generators: Architectures and Synthesis Method |
Shinobu Nagayama (Hiroshima City Univ.), Tsutomu Sasao (K.I.T), Jon T. Butler (Naval Postgraduate School) |
| (13) |
09:30-10:00 |
A Proposal of Design Support Tool for Genetic Algorithm Circuits on FPGA |
Tatsuhiro Tachibana, Yosihihiro Murata (NAIST), Naoki Shibata (Shiga Univ.), Keiichi Yasumoto, Minoru Ito (NAIST) |
| (14) |
10:00-10:30 |
A Genetic Approach for Reconfigurable Mesh Connected Processors |
Yusuke Fukushima, Masaru Fukushi, Susumu Horiguchi (Tohoku Univ.) |
Fri, Sep 16 AM
10:30 - 12:00 |
| (15) |
10:30-11:00 |
A method of low energy design over an autonomous reconfiguration technique |
Shigeki Imai, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| (16) |
11:00-11:30 |
Evaluation of Vth Control Region Granularity in Flex Power FPGA |
Masakazu Hioki, Takashi Kawanami (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
| (17) |
11:30-12:00 |
Implementation of Optimal Vth Assigning Algorithm in Flex Power FPGA |
Takashi Kawanami, Masakazu Hioki (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
| |
12:00-13:00 |
Lunch Break ( 60 min. ) |
Fri, Sep 16 PM
13:00 - 16:00 |
| (18) |
13:00-13:30 |
Cluster architecture for reconfigurable signal processing engine for wireless communications |
Miyoshi Saito, Hisanori Fujisawa (Fujitsu Ltd.), Nobuo Ujiie (FLT), Hideki Yoshizawa (Fujitsu Ltd.) |
| (19) |
13:30-14:00 |
A FPGA Based Hardware/Software Co-learning System |
Hoang Anh Tuan, Koichiro Nakamura, Shoichiro Namba, Katsuhiro Yamazaki, Shigeru Oyanagi (Ritsumeikan Univ.) |
| (20) |
14:00-14:30 |
Bio-Inspired Camera System with FPGA |
Yoshiki Yamaguchi, Noriyuki Aibe, Kazuya Hayashi (Univ. of Tsukuba), Yorihisa Yamamoto (Yamamoto System Design), Ikuo Yoshihara (Univ. of Miyazaki), Moritoshi Yasunaga (Univ. of Tsukuba) |
| (21) |
14:30-15:00 |
Discussion on FPGA Implementation of the Extended Euclidean Algorithm over GF(2^m) |
Takehiro Ito, Yuichiro Shibata, Ryuichi Harasawa, Kiyoshi Oguri (Nagasaki Univ) |
| (22) |
15:00-15:30 |
A method of determining dynamic reconfiguration timing of an FPGA-based encryption system by predicting the use of encryption algorithm |
Yuhei Niwa, Atusi Maeda, Yoshinori Yamaguchi (Univ. of Tsukuba) |
| (23) |
15:30-16:00 |
Evaluation of Arithmetic Precision Required for a Reconfigurable Raytracing Machine with Triangle Patches |
Shougo Nakamura, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 25 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| RECONF |
Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
|
| Contact Address |
Masahiro IIDA (Kumamoto Univ.)
E- : ii        -u
TEL: +81-96-342-3649 FAX: +81-96-342-3649 |
Last modified: 2005-08-01 11:54:41
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