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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2012-03-06
15:55		 Oita B-con Plaza Utilization of Register Transfer Level False Paths for Logic Optimization with Logic Synthesis Tools
Takehiro Mikami, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2011-130		 A circuit has many false paths on which signal transitions never affect its circuit behavior.This report proposes a logi... [more] VLD2011-130
pp.61-66
SAT, WBS
(Joint)		 2005-06-24
16:40		 Shizuoka Numazu Industry Promotion Plaza Performance Evaluation of a Symbol Synchronizer for MC-SS Systems Under Multi-path Environment
Takafumi Oya, Akira Ogawa (Meijo Univ.) 		In the multi-carrier spread spectrum (MC-SS) communications, it is necessary to synchronize the timing for Fast Fourier ... [more] WBS2005-7
pp.37-42
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