Print edition: ISSN 0913-5685
Online edition: ISSN 2432-6380
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RECONF2005-1
A Reconfigurable Embedded Decompressor for LSI Testing
Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 1 - 6
RECONF2005-2
Development of clustering tool to reduce area of chip and delay
Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 7 - 12
RECONF2005-3
Execution Cycle Minimization Algorithm for Dynamic Reconfigurable Processors with Hierarchical Memory Structure
Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
pp. 13 - 18
RECONF2005-4
Implementation of an SMT Processor and its Reconfigurable Cache with FPGA
Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo (Tokyo University of Agriculture and Technology)
pp. 19 - 24
RECONF2005-5
Improvement of Signature-based Phase Detection and its Application to Power Reduction in Caches
Yuya Ueno, Luong D. Hung (Tokyo Univ.), Masanori Takada, Daisuke Tashiro (Hitachi), Shuichi Sakai (Tokyo Univ.)
pp. 25 - 30
RECONF2005-6
[Invited Talk]
A general view on VLSI design methodology
Yukihiro Nakamura (Kyoto Univ.)
pp. 31 - 35
RECONF2005-7
Design of a Heap-tree Based Scalable Stochastic Biochemical Simulator on an FPGA
Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.)
pp. 37 - 42
RECONF2005-8
Scheduling of Rate Law Functions for an FPGA-based Biochemical Simulator
Naoki Iwanaga, Yuichiro Shibata (Nagasaki Univ.), Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano (Keio Univ), Akira Funahashi, Noriko Hiroi, Hiroaki Kitano (JST), Kiyoshi Oguri (Nagasaki Univ.)
pp. 43 - 48
RECONF2005-9
Implementation and Evaluation of Numerical Integrators on ReCSiP
Yasunori Osana, Masato Yoshimi, Yow Iwaoka (Keio Univ.), Akira Funahashi, Noriko Hiroi (ERATO-SORST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (ERATO-SORST), Hideharu Amano (Keio Univ.)
pp. 49 - 54
RECONF2005-10
Analyses of Operating Speed and Power Consumption in Flex Power FPGA
-- From Circuit Level To Chip Level --
Masakazu Hioki, Takashi Kawanami (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST)
pp. 55 - 60
RECONF2005-11
Area Overhead Estimation for Vth Control in Flex Power FPGA
Takashi Kawanami, Masakazu Hioki (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST)
pp. 61 - 66
RECONF2005-12
Reducing the Delay by Using the Small-World Network Structure
Hisashi Tsukiashi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 67 - 72
RECONF2005-13
Code Scheduling in Consideration of Place and Wire in Back End Compiler for PARS
Ryuji Hada, Takeshi Takeuchi, Takeshi Fukuda, Kazuya Tanigawa, Tetsuo Hironaka (HCU)
pp. 73 - 78
RECONF2005-14
A Simulation Platform for Evaluating Granularity of Self-Reconfigurable Device
Shin'ichi Kouyama, Futoshi Morie, Kentaro Nakahara (Kyoto Univ.), Tomonori Izumi (Ritsumeikan Univ.), Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.)
pp. 79 - 84