Print edition: ISSN 0913-5685
Online edition: ISSN 2432-6380
[TOP] | [2006] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [Japanese] / [English]
VLD2005-61
Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure
Kosuke Yabuki, Satoshi Ohtake, Hideo Fujiwara (NAIST)
pp. 1 - 6
VLD2005-62
A equidistant transition circuit for detecting path-delay faults
Hyonsu Cho, Takeo Yoshida (Univ. of the Ryukyus)
pp. 7 - 12
VLD2005-63
Reconfigurable Wrapper Design for Multi Clock Domain Cores Under Power Constraints
Yu Tanaka, Tomokazu Yoneda, Hideo Fujiwara (NAIST)
pp. 13 - 18
VLD2005-64
Minimal Set of Essential Lifetime Overlaps for Exploring 3D Schedule
Mineo Kaneko (JAIST)
pp. 19 - 24
VLD2005-65
A Consideration of Chaining methods on Behavioral Synthesis
Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ.)
pp. 25 - 30
VLD2005-66
A High-level Synthesis Algorithm Based on Floorplans for Distributed/Shared-Register Architectures
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 31 - 36
VLD2005-67
Pipelined Bipartite Modular Multiplication
Marcelo E. Kaihara, Naofumi Takagi (Nagoya Univ.)
pp. 37 - 42
VLD2005-68
no title
Keita Okubo, noname, noname, Takashi Kambe (noname)
pp. 43 - 48
VLD2005-69
Consideration on Delay Estimation Methods for Prefix Graphs
Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.)
pp. 49 - 54
VLD2005-70
Comparison of power consumption by form of adders
Takayuki Minakuchi, Shintaro Mimoto, Masayoshi Tachibana (KUT)
pp. 55 - 59
VLD2005-71
A Study of the Model and the Accuracy of Statistical Timing Analysis
Izumi Nitta, Katsumi Homma, Toshiyuki Shibuya (Fujitsu Lab.)
pp. 61 - 66
VLD2005-72
Fast Interconnect Delay Estimation with Considering Inductance Based on Multiple Regression Analysis
Kosei Suzuki, Marta D.Anwar, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 67 - 72
VLD2005-73
Deterministic/Probablistic Noise and Bit Error Rate Modeling on On-chip Global interconnect
Yoichi Yuyama, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)
pp. 73 - 78
VLD2005-74
Timing-Driven Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization
Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo)
pp. 79 - 84
VLD2005-75
Floorplan Design for 3D-VLSI
Hidenori Ohta (Tokyo Univ. of Agri. & Tech.), Toshinori Yamada (Saitama Univ.), Chikaaki Kodama, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. & Tech.)
pp. 85 - 90