IEICE Technical Report

Print edition: ISSN 0913-5685

Volume 106, Number 111

Circuits and Systems

Workshop Date : 2006-06-22 / Issue Date : 2006-06-15

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Table of contents

CAS2006-1
Area/delay Estimation for Application Processor
Daisuke Yamazaki, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 1 - 6

CAS2006-2
Modeling of Layout Dependent Copper Electrochemical Plating
Daisuke Fukuda, Hidetoshi Matsuoka, Toshiyuki Shibuya (FUJITSU LABORATORIES LTD.)
pp. 7 - 12

CAS2006-3
A CMOS Current Reference Independent of Deviation of Threshold Voltage
Masashi Negishi (Chuo Univ.), Kawori Takakubo (Meiji Univ.), Hajime Takakubo (Chuo Univ.)
pp. 13 - 18

CAS2006-4
A Design of Genotypes for Path Generation Using Genetic Algorithms
Jun Inagaki, Toshitada Mizuno, Tomoaki Shirakawa, Tetsuo Shimono (Hokkaido Tokai Univ.)
pp. 19 - 23

CAS2006-5
Solution Space Reduction of Sequence Pairs using Model Placement
Mineo Kaneko (JAIST)
pp. 25 - 28

CAS2006-6
Sequence-Pair Based Compaction under Equi-Length Constraint
Takehiko Matsuo (Univ. of Kitakyushu), Keiji Kida (Jedat), Tetsuya Tashiro, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 29 - 34

CAS2006-7
Re-placement Method for Circuit Modification
Kunihiko Yanagibashi, Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 35 - 40

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan