IEICE Technical Report

Print edition: ISSN 0913-5685

Reconfigurable Systems

Workshop Date : 2006-09-14 / Issue Date : 2006-09-07

RECONF2006-20
Optically Reconfigurable Gate Array with manufacturing defect tolerance
Ryo Hidaka, Minoru Watanabe, Fuminori Kobayashi (Kyutech)
pp. 1 - 5

RECONF2006-21
Reconfiguration speed and power consumption adjustment method for Optically Differential Reconfigurable Gate Arrays
Ryo Hidaka, Minoru Watanabe, Fuminori Kobayashi (Kyutech)
pp. 7 - 11

RECONF2006-22
An Optically Reconfigurable Gate Array with a liquid crystal hologram
Yoshiyuki Nakada, Minoru Watanabe, Fuminori Kobayashi (Kyutech)
pp. 13 - 16

RECONF2006-23
A logic design technique using SRAM blocks
Masayuki Sato, Hiroki Wakamatsu (Ｇｔｉ)
pp. 17 - 22

RECONF2006-24
Discussion of Memory-LSI Working as Reconfigurable Device
Masanori Yoshihara, Tetsuo Hironaka (HCU), Masayuki Sato (GTI)
pp. 23 - 28

RECONF2006-25
Yield enhancement of FPGAs with intra-die variation using multiple configuration data
Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST)
pp. 29 - 34

RECONF2006-26
[Special Invited Talk] How to Design FPGAs in a Nanometer Process
Kazutoshi Kobayashi (Kyoto Univ.)
pp. 35 - 40

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan