IEICE Technical Report

Print edition: ISSN 0913-5685

VLSI Design Technologies

Workshop Date : 2006-11-30 / Issue Date : 2006-11-23

VLD2006-72
On power and delay estimation method for LUT-based FPGAs
Ryuji Nakamura, Yusuke Matsunaga (Kyushu Univ.)
pp. 1 - 6

VLD2006-73
Architecture Design for Low-Power Multiplier applying Run Time Power Gating
Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T)
pp. 7 - 12

VLD2006-74
Physical Design for Low-Power Multiplier applying Run time Power Gating
Seidai Takeda, Toshihiro Kashima, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T.)
pp. 13 - 18

VLD2006-75
Design of High Speed Multiplier with Tree-structured partial product adders
Takayuki Minakuchi, Shintaro Mimoto, Masayoshi Tachibana (KUT)
pp. 19 - 23

VLD2006-76
Routability Driven Via Assignment and Routing for 2-Layer Ball Grid Array Packages
Yoichi Tomioka, Atsushi Takahashi (Tokyo Inst. of Tech)
pp. 25 - 30

VLD2006-77
On Handling Cell Placement with Adjacent Symmetry Constraints for Analog IC Layout Design
Shinichi Kouda, Kunihiro Fujiyoshi (TUAT)
pp. 31 - 36

VLD2006-78
Waveform measurment of LSI by using on-chip-probe
Shinichi Kawagoe, Masayoshi Tachibana (KUT)
pp. 37 - 41

VLD2006-79
Exploration of Communication Specifications in System Level Design
Kazutaka Kobayashi, Ryosuke Yamasaki, Norihiko Yoshida (Saitama Univ.), Shuji Narazaki (Nagasaki Univ.)
pp. 43 - 47

VLD2006-80
A Forwarding Unit Optimization Method for Application Processors
Toshihiro Hiura, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 49 - 54

VLD2006-81
Dual Core ASIP for High Speed Image Effect Processing
Takahiro Notsu (Osaka Univ.), Tastuhiro Yoshimura (AXELL), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
pp. 55 - 60

VLD2006-82
Development of A Secure Processor SEP-6 for non-contact type IC card
Daisuke Takahashi, Toshimitsu Inomata, Yoshikazu Arai, Masakazu Soga (IPU)
pp. 61 - 66

VLD2006-83
C-Base Design of a Particle Extraction System
Kenichi Jyoko, Hirokazu Uetsu, Hirotaka Nakazawa, Takashi Kambe (Kinki Univ)
pp. 67 - 72

VLD2006-84
A Hardware Algorithm for the Minimum p-quasi Clique Cover Problem
Shuichi Watanabe (The Grad. School, the Univ. of Aizu), Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (The Univ. of Aizu)
pp. 73 - 78

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan