Print edition: ISSN 0913-5685
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VLD2006-66
[Special Talk]
SystemVerilog Tutorial
Kasumi Hamaguchi (Panasonic), Takaaki Akashi (Synopsys), Takeharu Yui (ONW), Kenji Goto (Cadence), Miyuki Okamoto (SANYO), Masashi Sugiura (Zuken), Takehiko Tsuchiya (Toshiba), Yukio Chiwata (Fujitsu), Hirokuni Taketazu (Panasonic), KunDo Lee (Mentor), Yoshio Takamine (Renesas)
pp. 1 - 13
VLD2006-67
[Special Talk]
SAT Algorithms and its Applications (tentative)
Masahiro Fujita (Univ. of Tokyo)
pp. 15 - 20
VLD2006-68
Analysis of Maximum Switching Activities in Sequential Logic Circuits for Power Supply Integrity Validation
Hiroyuki Higuchi, Yuzi Kanazawa, Osamu Moriyama (Fujitsu Labs), Noriyuki Ito (Fujitsu)
pp. 21 - 26
VLD2006-69
Power Wave Smoothing by Clock Scheduling for Peak Power Reduction in LSI
Yosuke Takahashi, Atsushi Takahashi (Tokyo Tech)
pp. 27 - 32
VLD2006-70
A fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework
Yukihide Kohira (Tokyo Inst. of Tech), Atsushi Takahashi (Tokyo Inst.of Tech)
pp. 33 - 38
VLD2006-71
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Toshihiko Yokota (IBM JAPAN)
pp. 39 - 44
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.