IEICE Technical Report

Print edition: ISSN 0913-5685

Reconfigurable Systems

Workshop Date : 2007-01-17 / Issue Date : 2007-01-10

RECONF2006-56
Achieve a preprocessing part of auditory sense with circuit
Yuya Usami, Hidehiko Arai, Etu Sou, Kazushi Takahashi, Toshitaka Nagano, Masatoshi Sekine (TUAT)
pp. 1 - 6

RECONF2006-57
FGPA Implementation of the Computing System RAPLAS for Ray-Tracing
Daichi Zaitsu, Yoshiyuki Kaeriyama, Kenichi Suzuki, Ryusuke Egawa (Tohoku Univ.), Nobuyuki Ohba (IBM Japan, Ltd.), Tadao Nakamura (Tohoku Univ.)
pp. 7 - 12

RECONF2006-58
Face detection with the union of hardware and software
Masatoshi Yokokawa, Ichiro Sudo, Tomomi Yuno, Masatoshi Sekine (TUAT)
pp. 13 - 18

RECONF2006-59
Design of Residue Dividers Using Signed-Digit Number Residue Addition
Peng Jia, Shugang Wei (Gunma Univ.)
pp. 19 - 24

RECONF2006-60
GF(2^m) Digit-Serial Multiplier for Elliptic Curve Cryptosystem
Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Masao Yanagisawa, Satoshi Goto, Tatsuo Ohtsuki (Waseda Univ)
pp. 25 - 30

RECONF2006-61
A Parallel Algorithm Based on Genetic Algorithm and Tabu Search for LSI Floorplanning and Its Implementation on a PC Cluster
Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.)
pp. 31 - 36

RECONF2006-62
A Hardware Algorithm for the Quadratic Assignment Problem Based on Tabu Search Using FPGAs
Yoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ.)
pp. 37 - 42

RECONF2006-63
Converting PLC instruction sequence into logic circuit: implementation and evaluation
Masanori Akinaka, Shuichi Ichikawa (Toyohashi Univ. Tech.)
pp. 43 - 48

RECONF2006-64
On efficient cut enumeration in technology mapping for FPGA
Yusuke Matsunaga (Kyushu Univ.)
pp. 49 - 54

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan