Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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RECONF2007-15
Proposal and application of Memory with Digit-Width Converter
Yuhki Yamabe, Kazuya Tanigawa, Tetsuo Hironaka (HCU)
pp. 1 - 6
RECONF2007-16
Implementation of Memory (MPLD) with The Ability to work as a Reconfigurable Device
Masanori Yoshihara, Naoki Hirakawa, Kazuya Tanigawa, Tetsuo Hironaka (HCU), Masayuki Sato (GTI)
pp. 7 - 12
RECONF2007-17
Consideration about Routing Resources for DS-HIE Architecture
Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (HCU)
pp. 13 - 18
RECONF2007-18
Multi-context optically reconfigurable gate array
Naoki Yamaguchi, Minoru Watanabe (Shizuoka Univ.)
pp. 19 - 22
RECONF2007-19
A fast optical reconfiguration under an operation of a gate array in an ODRGA-VLSI
Mao Nakajima, Minoru Watanabe (Shizuoka Univ.)
pp. 23 - 27
RECONF2007-20
Measurement for reconfiguration and retention time of a dymaic optically reconfigurable architecture
Daisaku Seto, Minoru Watanabe (Shizuoka Univ.)
pp. 29 - 33
RECONF2007-21
[Invited Talk]
Reconfigurable Architecture for Car Tuners
Makoto Ozone, Katsunori Hirase, Kazuhisa Iizuka, Tatsuo Hiramatsu (SANYO), Shinji Kimura (Waseda Univ.)
pp. 35 - 40
RECONF2007-22
A Study of Performance-driven Simultaneous Clustering and Placement for FPGA
Hiroshi Shinohara, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 41 - 46
RECONF2007-23
Hardware/Software Partitioning for SoPC based Embedded Systems
Kenichi Shimada (NEC Electronics), Masaru Fukushi, Susumu Horiguchi (Tohoku Univ.)
pp. 47 - 52
RECONF2007-24
Dynamically Reconfigurable Protocol Transducer Synthesis for utilizing IPs
Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita (Tokyo Univ.)
pp. 53 - 58
RECONF2007-25
[Special Talk]
Technology Trends in Reconfigurable Logic Circuit
Takayuki Kaneda (JPO)
pp. 59 - 64
RECONF2007-26
A Study on Multibyte Processing for NFA-based Pattern Matching Circuits
Norio Yamagaki, Satoshi Kamiya (NEC Corp.)
pp. 65 - 70
RECONF2007-27
Pipeline MD5 Implementations on FPGA with Data Forwarding
Hoang Anh Tuan, Katsuhiro Yamazaki, Shigeru Oyanagi (Ritsumeikan Univ)
pp. 71 - 76
RECONF2007-28
Performance Evaluation of Dynamic-Reconfigurable Processor MuCCRA-1 with Various Applications
Adepu Parimala, Yohei Hasegawa, Vasutan Tunbunheng, Hideharu Amano (Keio Univ.)
pp. 77 - 82
RECONF2007-29
Dynamic Reconfigurable Processor with direct execution mode
Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio univ)
pp. 83 - 88
RECONF2007-30
Representing dynamically reconfigurable architectures for placement and routing based on graphs with configuration information
Vasutan Tunbunheng, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.)
pp. 89 - 94
RECONF2007-31
An Energy Reduction Technique with Dynamic Frequency Scaling Control for Dynamically Reconfigurable Processor Arrays
Satoshi Tsutsumi, Yohei Hasegawa, Takashi Nishimura, Hideharu Amano (Keio Univ.)
pp. 95 - 100
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.