IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Computer Systems

Workshop Date : 2007-10-25 - 2007-10-26 / Issue Date : 2007-10-18

CPSY2007-24
The application of the massively parallel processor based on the matrix architecture
Katsuya Mizumoto, Hiroyuki Yamasaki, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Masami Nakajima, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas)
pp. 1 - 5

CPSY2007-25
The program development method of the massively parallel processor based on the matrix architecture.
Hiroyuki Yamasaki, Katsuya Mizumoto, Hideyuki Noda, Tetsu Nishijima, Kanako Yoshida, Takeaki Sugimura, Takashi Kurafuji, Osamu Yamamoto, Yoshihiro Okuno, Kazutami Arimoto (Renesas)
pp. 7 - 12

CPSY2007-26
An Implementation and evaluation of Ant Colony Optimization for massively parallel SIMD processor MX Core
Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ)
pp. 13 - 18

CPSY2007-27
Acceleration of Multimedia Data Processing with CAM-Enhanced Massive-Parallel SIMD Matrix Processor
Takeshi Kumaki, Masakatsu Ishizaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yasuto Kuroda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito (Renesas Technology)
pp. 19 - 24

CPSY2007-28
Acceleration of AES Encryption with CAM-Enhanced Massive-Parallel SIMD Matrix Processor
Masakatsu Ishizaki, Takeshi Kumaki, Masaharu Tagami, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Takayuki Gyohten, Hideyuki Noda, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology)
pp. 25 - 30

CPSY2007-29
[Special Invited Talk] Utilization of FPGA based devices for very high-speed internet communications
Kei Hiraki, Yutaka Sugawara, Takeshi Yoshino, Mary Inaba (Univ. of Tokyo)
pp. 31 - 32

CPSY2007-30
An examination of hardware acceleration in FPGA placement based on SA
Yoshio Sonokawa, Yuji Ariuchi, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 33 - 38

CPSY2007-31
Performance, Power, and Dependability Trade-off on Multiple Clusterd Core Processors
Toshinori Sato (Kyushu Univ.), Toshimasa Funaki (Kyushu Inst Tech)
pp. 39 - 44

CPSY2007-32
PSI-NSIM: A Parallel Interconnection Network Simulator for Performance Analysis of Large-scale Parallel Systems
Hidetomo Shibamura (ISIT), Ryutaro Susukita (Fukuoka IST), Hiroaki Honda, Yuichi Inadomi, Yunqing Yu, Koji Inoue, Mutsumi Aoyagi (Kyushu Univ.)
pp. 45 - 50

CPSY2007-33
Routing Performance Evaluation for Stationary End Nodes in Ad Hoc Network
Takuo Nakashima (Kyushu Tokai University/Kumamoto Univ.), Toshinori Sueyoshi (Kumamoto University)
pp. 51 - 56

CPSY2007-34
Kernel Protection Mechanism of Dynamic Running Mode Switch of Application Program for AnT
Tadato Nishina, Masanori Umemoto, Hideo Taniguchi (Okayama Univ.), Kazutoshi Yokoyama (NTT DATA)
pp. 57 - 62

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan