Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2006] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [Japanese] / [English]
DC2007-44
Comparison between STA and SSTA results in microprocessor design
Noriyuki Ito, Hiroaki Komatsu, Hiroyuki Sugiyama, Naomi Bizen, Katsumi Iguchi, Yuji Yoshida (Fujitsu)
pp. 1 - 6
DC2007-45
A New Technique for Elimination of Irregular Data in Measured Values
-- A Data Screening Technique Appling Skewness of Basic Statistic --
Shin-ichi Ohkawa, Hiroo Masuda (Renesas)
pp. 7 - 12
DC2007-46
A Study of Grid-Based Modeling of Spatially Correlated Manufacturing Variability for SSTA
Shinyu Ninomiya, Masanori Hashimoto (Osaka Univ.)
pp. 13 - 17
DC2007-47
Highly Extensible Base Processors for Short-term ASIP Design
Hirofumi Iwato, Takuji Hieda, Hiroaki Tanaka (Osaka Univ.), Jun Sato (Tsuruoka NCT), Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.)
pp. 19 - 24
DC2007-48
Complexities and Algorithms of Minimum-Delay Compensation Problems in Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST)
pp. 25 - 30
DC2007-49
A Schedule Improvement with Skew Control in Datapath Synthesis
Takayuki Obata, Mineo Kaneko (JAIST)
pp. 31 - 36
DC2007-50
Necessary and Sufficient Conditions for Symmetry Placements
Kunihiro Fujiyoshi, Chikaaki Kodama, Shinichi Koda (TUAT)
pp. 37 - 41
DC2007-51
Improved Method of Rectilinear Block Packing Based on O-Tree Representation
Hidehiko Ukibe, Kunihiro Fujiyoshi (TUAT)
pp. 43 - 48
DC2007-52
Parallel prefix adder synthesis based on Ling’s carry computation
Taeko Matsunaga, Shinji Kimura (Waseda Univ.), Yusuke Matsunaga (Kyushu Univ.)
pp. 49 - 54
DC2007-53
An Efficient Behavioral Synthesis Method Considering Specialized Functional Units
Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ.)
pp. 55 - 60
DC2007-54
A Hardware Engine for Generation Deformed Map
Akira Arahata, Ryuta Nara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 61 - 66
DC2007-55
An LDPC Decoder Based on the Min-Sum Algorithm for High Speed WLAN Systems
Nozomu Hama, Hiroyuki Shimajiri, Takeo Yoshida (Univ. of the Ryukyus)
pp. 67 - 72
DC2007-56
Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
pp. 73 - 78
DC2007-57
Cycle Partitioned Scheduling for Code Optimization of VLIW DSP
Yuuki Masui, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 79 - 84
DC2007-58
Retargetable Linear Assembler for VLIW Processor
Satoshi Nogaito, Nagisa Ishiura (Kwansei Gakuin Univ.), Masaharu Imai (Osaka Univ.)
pp. 85 - 90
DC2007-59
Memory Assignment Method Considering Orders of Operands for Massively Parallel Fine-grained SIMD Processor
Akira Kobashi, Ittetsu Taniguchi, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas)
pp. 91 - 96
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.