IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2008-09-25 - 2008-09-26 / Issue Date : 2008-09-18

RECONF2008-23
Acceleration of two-dimensional liquid simulation using FPGAs
Anna Sato, Yuichi Okuyama (Aizu Univ), Tsuyoshi Hamada (Nagasaki Univ), Junji Kitamichi, Kenichi Kuroda (Aizu Univ)
pp. 1 - 6

RECONF2008-24
Implementation of JPEG Encoder on Dynamically Reconfigurable Processor and its Evaluation
Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ)
pp. 7 - 12

RECONF2008-25
An Implementation of road sign recognition algorithm using levenshtein distance on FPGA
Souichi Shimizu (Keio Univ.), Yoshiaki Ajioka (Ecchandesu Inc.), Masatoshi Arai, Daisuke Konno, Tomomichi Nanba (CalsonicKansei Co.), Hideharu Amano (Keio Univ.)
pp. 13 - 20

RECONF2008-26
An automatic combine algorithm of arithmetic pipelines for an FPGA-based biochemical simulator focused on similarities of rate law functions
Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata (Nagasaki Univ.), Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi (Keio Univ.), Noriko Hiroi (EMBL-EBI), Kiyoshi Oguri (Nagasaki Univ.)
pp. 21 - 26

RECONF2008-27
A Proposal of the Network Switch for a PC cluster that can change connection of Distributed Shared Memory
Yoshimasa Ohnishi, Takaichi Yoshida (Kyushu Institute of Tech.)
pp. 27 - 32

RECONF2008-28
A Hardware Evaluation System for 2D Interconnection Networks by using an FPGA Based Network Card
Akira Uejima, Masaki Kohata (Okayama Univ. of Sci.)
pp. 33 - 38

RECONF2008-29
An Implementation of Operating System Functions for a Distributed FPGA Cluster System
Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 39 - 44

RECONF2008-30
[Invited Talk] Operating System and Reconfigurable Hardware
Hideo Taniguchi (Okayama Univ.)
pp. 45 - 50

RECONF2008-31
A measurement of retention time of a dynamic optically reconfigurable gate array with large gates
Daisaku Seto, Minoru Watanabe (Shizuoka Univ.)
pp. 51 - 56

RECONF2008-32
Development of Digit-serial Floating Point Units for Scientific Computation Engine
Taiga Ban, Yu Shiraishi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 57 - 62

RECONF2008-33
Exploration of Input Granularity Optimization for Variable Grain Logic Cell
Masahiro Koga, Hiroshi Miura, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 63 - 68

RECONF2008-34
Practice Evaluation Dynamically Reconfigurable Processor MuCCRA-2β
Yoshiki Saito, Masaru Kato, Shotaro Saito, Toru Sano, Keiichiro Hirai, Takashi Nishimura, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ.)
pp. 69 - 74

RECONF2008-35
A Case Study of Reliable Softcore Processor Using TMR Technique
Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 75 - 80

RECONF2008-36
A study of a fault-tolerant System using TFT method
Atsuhiro Kanamaru, Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Univ. of Tsukuba)
pp. 81 - 86

RECONF2008-37
Consideration of Combinational Circuit Mapping Method for Reconfigurable Device MPLD
Yutaro Oda, Kazuya Tanigawa, Tetsuo Hironaka, Naoki Hirakawa, Hiroaki Toguchi (Hiroshima City Univ.), Masayuki Sato (Taiyo Yuden)
pp. 87 - 92

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan