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| Presentation | 2008-09-26 10:30 Exploration of Input Granularity Optimization for Variable Grain Logic Cell Masahiro Koga, Hiroshi Miura, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)  RECONF2008-33 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Intellectual Property (IP) core. However, conventional RLDs,which are commercial Field Programmable Gate Arrays (FPGAs), cannot achieve efficient implementation. Then, we have studied a reconfigurable logic architecture that has both flexibility and high performance as a reconfigurable IP core. In this paper,we evaluate the granularity of BLE using our technology mapping tool. As a result, best result for area is achieved by 3 inputs BLE, and for logic depth is achieved by 5 inputs BLE. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | reconfigurable IP / coarse-grain / fine-grain / technology mapping / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 220, RECONF2008-33, pp. 63-68, Sept. 2008. | |
| Paper # | RECONF2008-33 | |
| Date of Issue | 2008-09-18 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2008-33 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2008-09-25 - 2008-09-26 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okayama Univ. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2008-09-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Exploration of Input Granularity Optimization for Variable Grain Logic Cell |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable IP |
| Keyword(2) | coarse-grain |
| Keyword(3) | fine-grain |
| Keyword(4) | technology mapping |
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| Keyword(8) | |
| 1st Author's Name | Masahiro Koga |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 2nd Author's Name | Hiroshi Miura |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 4th Author's Name | Masahiro Iida |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 5th Author's Name | Toshinori Sueyoshi |
| 5th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2008-09-26 10:30:00 |
| Presentation Time | 30 minutes |
| Registration for | RECONF |
| Paper # | RECONF2008-33 |
| Volume (vol) | vol.108 |
| Number (no) | no.220 |
| Page | pp.63-68 |
| #Pages | 6 |
| Date of Issue | 2008-09-18 (RECONF) |
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