Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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ICD2008-17
Branch Target Predictor Utilizing Context Base Value Predictor
Tetsurou Hirashima (NRI), Hajime Shimada (Kyoto Univ.), Shinobu Miwa (TUAT), Shinji Tomita (Kyoto Univ.)
pp. 1 - 6
ICD2008-18
Speculation scheme that continues executing mispredicted instructions
Takanobu Kita, Ryota Shioya, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai (Univ. of Tokyo)
pp. 7 - 12
ICD2008-19
Evaluation of Area-Oriented Register Cache
Ryota Shioya (Univ. Tokyo), Hidetsugu Irie (JST), Masahiro Goshima, Shuichi Sakai (Univ. Tokyo)
pp. 13 - 18
ICD2008-20
An Evaluation of Barrier Synchronization Mechanism Considering Hierarchical Processor Grouping
Kaito Yamada (Hitachi), Masayoshi Mase, Jun Shirako, Keiji Kimura (Waseda Univ.), Masayuki Ito, Toshihiro Hattori (Renesas), Hiroyuki Mizuno, Kunio Uchiyama (Hitachi), Hironori Kasahara (Waseda Univ.)
pp. 19 - 24
ICD2008-21
[Invited Talk]
Multi - Core Processor for Computer System
Yoshio Miki (HITACHI)
pp. 25 - 28
ICD2008-22
[Invited Talk]
Cell Broadband Engine and SpursEngine as a Muti-core Processor
Hiroo Hayashi (Toshiba Corp.)
pp. 29 - 34
ICD2008-23
[Invited Talk]
Intel's vision
-- The Demand for Many Cores: Tera-Scale Usage Models --
Yoshie Munakata (Intel)
pp. 35 - 36
ICD2008-24
[Panel Discussion]
What We Have To Do in Multi-Core Era?
Shinji Tomita (Kyoto Univ.), Naoki Nishi (NEC), Mitsuo Saito (Toshiba), Yoshie Munakata (Intel), Aiichiro Inoue (Fujitsu), Toshiyuki Sanuki (IBM Japan), Yasushi Fukunaga (Hitachi)
pp. 37 - 38
ICD2008-25
A Scalable Multi-core Processor for Mobile Multimedia Applications
Hiroyuki Usui, Shuou Nomura, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Jun Tanabe, Masato Uchiyama, Takashi Miyamori, Yoshiro Tsuboi (Toshiba)
pp. 39 - 44
ICD2008-26
Design and Evaluation of a Heterogeneous Multicore SoC with 9 CPUs and 2 Matrix Processors
Masami Nakajima, Koichi Ishimi, Naoto Okumura, Norio Masui, Osamu Yamamoto, Hiroyuki Kondo (Renesas)
pp. 45 - 50
ICD2008-27
PSI-SIM: Performance Prediction for Peta-Scale Supercomputers with Thousands of Multi-core Processors
Koji Inoue (Kyushu Univ.), Ryutaro Susukita (IST), Hisashige Ando, Shigeru Ishizuki, Hidemi Komatsu (Fujitsu), Yuichi Inadomi, Hiroaki Honda (Kyushu Univ.), Shuji Yamamura (Fujitsu), Hidetomo Shibamura (ISIT), Yunqing Yu, Mutsumi Aoyagi (Kyushu Univ.), Yasunori Kimura (Fujitsu), Kazuaki Murakami (Kyushu Univ.)
pp. 51 - 56
ICD2008-28
Design of a Multi-Context Field-Programmable VLSI Using Ferroelectric-Based Functional Pass-Gates
Noriaki Idobata, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 57 - 62
ICD2008-29
Architecture of a Stereo Matching VLSI Based on Recursive Computation
Keita Tanji, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 63 - 68
ICD2008-30
Automatic Parallelization of Restricted C Programs using Pointer Analysis
Masayoshi Mase (Waseda Univ.), Daisuke Baba (Waseda Univ. / Matsushita Electric Industrial), Harumi Nagayama (Waseda Univ. / Intel), Yuta Murata, Keiji Kimura, Hironori Kasahara (Waseda Univ.)
pp. 69 - 74
ICD2008-31
Performance Balancing: An Efficient Helper-Thread Execution on CMPs
Kenichi Imazato, Naoto Fukumoto, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
pp. 75 - 80
ICD2008-32
Adaptive Management of Parallelism on Transactional Memories
Susumu Takeda, Keita Shimasaki, Koji Inoue, Kazuaki Murakami (kyushu Univ.)
pp. 81 - 86
ICD2008-33
A Fine Grain Dynamic Sleep Control Scheme in Superscalar Processor
Yu Kojima, Daisuke Ikebuchi, Naomi Seki, Yohei Hasegawa, Hideharu Amano (Keio Univ.), Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami (Shibaura Inst of Tech), Tetsuya Sunada, Jun Kanai, Mitaro Namiki (Tokyo Univ. of Agri & Tech), Masaaki Kondo, Hiroshi Nakamura (Univ. of Tokyo)
pp. 87 - 92
ICD2008-34
Considering Performance and Area Overhead in DVS System Utilizing Input Variations
Yuji Kunitake (Kyushu U.), Toshinori Sato (Fukuoka U.), Hiroto Yasuura (Kyushu U.)
pp. 93 - 98
ICD2008-35
A Low-Latency On-Chip Router Architecture with Prediction Mechanism
Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.), Tsutomu Yoshinaga (UEC)
pp. 99 - 104
ICD2008-36
Performance Balancing: An Implementation of Efficient On-chip Memory Hierarchy on Cell/B.E.
Tetsuo Hayashi, Naoto Fukumoto, Kenichi Imazato, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
pp. 105 - 110
ICD2008-37
Quantitative Analysis of Memory Workload on Chip-Multiprocessors
Mitsuaki Yamaguchi, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)
pp. 111 - 116
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.