IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 108, Number 361

Computer Systems

Workshop Date : 2008-12-18 / Issue Date : 2008-12-11

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Table of contents

CPSY2008-43
A Control System on Response Time of a Security Realization Method using a General Purpose OS on a Multi-Hop Wireless Network
Mihoko Uno, Masato Oguchi (Ocha Univ.)
pp. 1 - 6

CPSY2008-44
Extraction of Characteristics of Anomaly Accessed IP Packets using Chi-square Method
Shunsuke Oshima (Yatsushiro National College of Tech.), Nakashima Takuo (Tokai Univ.), Toshinori Sueyoshi (Kumamoto Univ.)
pp. 7 - 12

CPSY2008-45
A Task Clustering Minimizing Worst Response Time in Distributed Processing Environment
Hidehiro Kanemitsu, Yi Lu, Yoshihiro Otani, Gilhyo Lee, Hidenori Nakazato, Takashige Hoshiai, Yoshiyori Urano (Waseda Univ.)
pp. 13 - 18

CPSY2008-46
Analyzing characteristics of PC cluster consolidated with IP-SAN in the execution of data-intensive applications
Asuka Hara (Ochanomizu Univ.), Kikuko Kamiasaka (NICT), Saneyasu Yamaguchi (Kogakuin Univ.), Masato Oguchi (Ochanomizu Univ.)
pp. 19 - 24

CPSY2008-47
The Dynamic Memory Management for Distributed Large Memory System DLM
Kazuhiro Saito, Hiroko Midorikawa, Munenori Kai (Seikei Univ.)
pp. 25 - 30

CPSY2008-48
[Special Invited Talk] An Introduction of Our Recent Research on VLIW from 3way to 9Nway
Yasuhiko Nakashima (NAIST)
pp. 31 - 36

CPSY2008-49
Evaluation of iSCSI remote storage access in long latency with analysis of congestion window and packets
Reika Higa (Ocha Univ), Kosuke Matsubara, Takao Okamawari (SOFTBANK MOBILE), Saneyasu Yamaguchi (Kogakuin), Masato Oguchi (Ocha Univ)
pp. 37 - 42

CPSY2008-50
Network cache system with the autonomic recovery mechanism for wide-area SAN
Takahiro Miyamoto, Michiaki Hayashi, Hideaki Tanaka (KDDI Labs)
pp. 43 - 48

CPSY2008-51
A Reconfigurable Processor for Genetic Algorithm based on Redundant Binary Number
Masanao Aoshima, Akinori Kanasugi (Tokyo Denki Univ.)
pp. 49 - 54

CPSY2008-52
An Architecture of Dynamically Reconfigurable Systolic Array and FPGA Implementation
Toshiyuki Ishimura, Yuhki Hayakawa, Akinori Kanasugi (Tokyo Denki Univ.)
pp. 55 - 60

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan