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Paper Abstract and Keywords
Presentation 2008-12-18 13:15
[Special Invited Talk] An Introduction of Our Recent Research on VLIW from 3way to 9Nway
Yasuhiko Nakashima (NAIST) CPSY2008-48
Abstract (in Japanese) (See Japanese page) 
(in English) The first VLIW revealed as a hardware structure that could directly execute horizontal micro codes has been raised to one of the major machine codes with the advance of compiler technology, and several modern processors have come to employ VLIW structure to improve energy-delay product. Despite the difficulty in becoming popular due to lack of binary compatibility in opposition to superscalars, VLIW may be used to organize unique processors. In this talk, the idea and the status of our recent research on three types of VLIW are disclosed. In the first talk entitled `A 5way ARM compatible processor equipped with instruction decomposition,' a combination of an instruction decomposition technique and a self-stabilized circuitry that may mitigate the increasing fault ratio in the future device technology is described. In the second talk entitled `A 9way heterogeneous SMT processor,' the structure of a novel processor architecture that fuses the backend pipelines including data cache designed for different types of instruction set architecture, and the result of implementation by FPGA and standard cells are described. Such architecture may be a solution for decreasing the cost of a modern heterogeneous multiprocessor system that should integrate de facto platforms and some original features. In the final talk entitled `A 9Nway linear array pipeline processor,' an idea for opening a path for VLIW that suffers from binary compatibility and a reconfigurable data path that suffers from software productivity is described. The key idea is to combine VLIW decoders with a reconfigurable network. From the view of the former, hardware may find a large amount of instructions to execute in parallel. From the view of the latter, a reconfigurable data path may exploit the state-of-the-art VLIW compiler technique.
Keyword (in Japanese) (See Japanese page) 
(in English) VLIW / Heterogeneous SMT / Linear Array / Reconfigurable Data Path / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 361, CPSY2008-48, pp. 31-36, Dec. 2008.
Paper # CPSY2008-48 
Date of Issue 2008-12-11 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY  
Conference Date 2008-12-18 - 2008-12-18 
Place (in Japanese) (See Japanese page) 
Place (in English) KYOTO Research Park 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Network Storage Systems, etc. 
Paper Information
Registration To CPSY 
Conference Code 2008-12-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Introduction of Our Recent Research on VLIW from 3way to 9Nway 
Sub Title (in English)  
Keyword(1) VLIW  
Keyword(2) Heterogeneous SMT  
Keyword(3) Linear Array  
Keyword(4) Reconfigurable Data Path  
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1st Author's Name Yasuhiko Nakashima  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2008-12-18 13:15:00 
Presentation Time 60 minutes 
Registration for CPSY 
Paper # CPSY2008-48 
Volume (vol) vol.108 
Number (no) no.361 
Page pp.31-36 
#Pages 6 
Date of Issue 2008-12-11 (CPSY) 

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