IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Computer Systems

Workshop Date : 2010-11-30 - 2010-12-01 / Issue Date : 2010-11-23

CPSY2010-32
A case study of the effective value range analysis for Behavioral synthesis
Kenji Tomonaga, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 1 - 6

CPSY2010-33
Examination of the virtual wiring for an ASIC emulator using high-speed serial communication
Toshio Yabuta, Yoshihiro Ichinomiya, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 7 - 12

CPSY2010-34
A Router Architecture for Priority-Aware On-Chip Networks
Takuma Kogo, Nobuyuki Yamasaki (Keio Univ)
pp. 13 - 18

CPSY2010-35
A discussion on calculating eigenvalues of real symmetric tridiagonal matrices on a GPU
Kohei Matsunobu, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ)
pp. 19 - 24

CPSY2010-36
A Study of Comparison between In-order and Out-of-order Processor for Many-core Processor Era
Takefumi Miyoshi, Hidetsugu Irie, Yuuki Matsumura, Tsutomu Yoshinaga (UEC)
pp. 25 - 30

CPSY2010-37
Preliminary Evaluation of Automatic Thread-Level Parallelization using Binary-Level Variable Analysis
Takashi Shiroto, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.)
pp. 31 - 36

CPSY2010-38
Reliable Digital Signal Transmission Methodology -- Its Application to the High Speed Bass Line --
Shohei Akita, Hiroki Shimada, Masami Ishiguro, Noriyuki Aibe, Moritoshi Yasunaga (Univ. of Tsukuba), Ikuo Yoshihara (Miyazaki Univ.)
pp. 37 - 42

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan