IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Dependable Computing

Workshop Date : 2011-04-12 / Issue Date : 2011-04-05

DC2011-1
An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults
Satoshi Fukumoto, Kenta Imai, Hideo Kohinata, Masayuki Arai (Tokyo Metropolitan Univ.)
pp. 1 - 4

DC2011-2
A Note on Data Compression of Double-Precision Floating-Point Numbers for Massively Parallel Numerical Simulations
Mamoru Ohara, Takashi Yamaguchi (TIRI)
pp. 5 - 10

DC2011-3
A Case Study on Dependable Network-on-Chip Platform for Automotive Applications
Chammika Mannakkara, Daihan Wang, Vijay Holimath, Tomohiro Yoneda (NII)
pp. 11 - 16

DC2011-4
[Invited Talk] Tamper LSI Design Methodology Resistant to Malicious Attack
Takeshi Fujino, Mitsuru Shiozaki (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Univ.)
pp. 17 - 22

DC2011-5
Transient-Fault-Tolerant Out-of-Order Superscalar Processor
Satoshi Arima, Takashi Okada, Ryota Shioya, Masahiro Goshima, Shuichi Sakai (The Univ. of Tokyo)
pp. 23 - 28

DC2011-6
Note on Defect Level Evaluation of Cascaded TMR for Pipeline Processors
Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metro. Univ.)
pp. 29 - 34

DC2011-7
Highly Flexible Task Tracer IP for the Real-Time OS on FPGA/SoC Environments
Yuji Takeda, Mamoru Ohara, Tadashi Okabe, Ken Sato (Tokyo Metro. Indust. Tech. Res. Inst.)
pp. 35 - 40

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan