IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 111, Number 216

VLSI Design Technologies

Workshop Date : 2011-09-26 - 2011-09-27 / Issue Date : 2011-09-19

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Table of contents

VLD2011-40
A transistor-level symmetrical layout generation method for analog device
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 1 - 4

VLD2011-41
CMOS Op-amp Circuit Synthesis with Geometric Programming Models for Layout-Dependent Effects
Yu Zhang, Gong Chen, Qing Dong, Jing Li, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 5 - 10

VLD2011-42
MSA: Mixed Stochastic Algorithm for Placement with Larger Solution Space
Yiqiang Sheng (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.), Shuichi Ueno (Tokyo Inst. of Tech.)
pp. 11 - 16

VLD2011-43
Analytical Placement for Closed-Symmetrical Placement
Yasuhiro Takashima, Yusuke Oya (Univ. of Kitakyushu)
pp. 17 - 22

VLD2011-44
On set pair routing problem
Atsushi Takahashi (Osaka Univ.)
pp. 23 - 28

VLD2011-45
[Invited Talk] Bondage: A legal interconnect to define a reasonable placement
Yoji Kajitani (Univ. of Kitakyushu)
pp. 29 - 30

VLD2011-46
A Reconfigurable Layout Method and Evaluation for Network on Chip
Yuichi Nakamura (NEC)
pp. 31 - 36

VLD2011-47
Evaluation of Net-based Move in Placement for a Memory-based Reconfigurable Device MPLD
Masato Inagi, Masatoshi Nakamura, Tetsuo Hironaka (Hiroshima City Univ.), Takashi Ishiguro (Taiyo Yuden)
pp. 37 - 42

VLD2011-48
A Design Method of Network-on-Chip Architecture for FPGA
Hideki Katabami, Hiroshi Saito (Aizu Univ.)
pp. 43 - 48

VLD2011-49
A statistical evaluation of approximate methods for soft error tolerance analysis of combinational circuits
Hidenori Ayabe, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.)
pp. 49 - 54

VLD2011-50
Acceleration of Smith-Waterman Algorithm using a Pipelined Array Processor
Asuka Tanaka, Shizuka Ishikawa, Toshiaki Miyazaki (Univ. of Aizu)
pp. 55 - 59

VLD2011-51
Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis
Keisuke Inoue, Mineo Kaneko (JAIST)
pp. 61 - 66

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan