IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2011-05-18 - 2011-05-19 / Issue Date : 2011-05-11

VLD2011-1
Study of the slew-rate contorol system for reducing far-end crosstalk
Kazunori Nakashima, Suguru Kato, Shinichi Sasaki (Saga Univ)
pp. 1 - 6

VLD2011-2
An Effective Overlap Removable Objective for Analytical Placement
Syota Kuwabara, Yukihide Kohira (Univ. of Aizu), Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 7 - 12

VLD2011-3
Path Encoding Method for High Speed Frequency-Mapping Associative Memory
Seiryu Sasaki, Masahiro Yasuda, Akio Kawabata, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.)
pp. 13 - 18

VLD2011-4
[Invited Talk] Recent Gating-Techniques for Power Reduction
Kimiyoshi Usami (Shibaura Inst. of Tech.)
pp. 19 - 24

VLD2011-5
[Invited Talk] Low Power Design Technology on Algorithm/Architecture Level for Video Processing
Satoshi Goto (Waseda Univ.)
pp. 25 - 26

VLD2011-6
Super-resolution by UsingWeighted Adders with Selector Logics
Hiromine Yoshihara, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.)
pp. 27 - 32

VLD2011-7
Multi-Stage Power Gating Based on Controlling Values of Logic Gates
Jin Yu, Shinji Kimura (Waseda Univ.)
pp. 33 - 38

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan