IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 117, Number 171

Superconductive Electronics

Workshop Date : 2017-08-09 / Issue Date : 2017-08-02

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Table of contents

SCE2017-11
Demonstration of Quantum Flux Parametron without DC Offset Currents using Ferromagnets
Hayato Iwashita, Hiroshi Ito, Soya Taniguchi, Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.)
pp. 1 - 5

SCE2017-12
Energy evaluation of the feedback latch using AQFP logic
Mai Nozoe, Naoki Takeuti, Christopher Ayala, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.)
pp. 7 - 12

SCE2017-13
Yield Evaluation of 90k Junction-scale Adiabatic Quantum-Flux-Parametron Circuits
Fumihiro China, Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa (YNU)
pp. 13 - 18

SCE2017-14
Evaluation of a random access memory cell composed of quantum flux parametron
Hiroshi Takayama, Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.)
pp. 19 - 23

SCE2017-15
Design and evaluation of 2 × 2 look-up table and extension to 4 × 4 for realization of FPGA using single flux quantum circuits
Mika Araki, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.)
pp. 25 - 29

SCE2017-16
Demonstration of AQFP/CMOS hybrid system and design and measurement of an AQFP 16-bit MUX
Yukihiro Okuma, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.)
pp. 31 - 36

SCE2017-17
Design of Component Circuits for Rapid Single-Flux-Quantum Gate-Level-Pipelined Microprocessors
Yuki Hatanaka, Yuichi Matsui, Masamitsu Tanaka, Kyosuke Sano, Akira Fujimaki (Nagoya Univ.), Koki Ishida, Takatsugu Ono, Koji Inoue (Kyushu Univ.)
pp. 37 - 42

SCE2017-18
Improvement of double oscillator type SFQ time-to-digital converter and realization of high temporal resolution
Yuma Tomitsuka, Yutaka Abe (Yokohama National Univ.), Nobuyuki Zen (NAIST), Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.)
pp. 43 - 48

SCE2017-19
Design of Digital SQUID using sub-SFQ Feedback with High Sampling Rate
Kosuke Okabe, Masato Naruse, Tohru Taino, Hiroaki Myoren (Saitama Univ.)
pp. 49 - 53

SCE2017-20
Design of Low-latency SFQ Up/Down Counter for Digital Signal Processing
Ryotaro Kamiya, Masato Naruse, Tohru Taino, Hiroaki Myoren (Saitama Univ.)
pp. 55 - 59

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan