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Paper Abstract and Keywords
Presentation 2017-08-09 14:35
Design of Component Circuits for Rapid Single-Flux-Quantum Gate-Level-Pipelined Microprocessors
Yuki Hatanaka, Yuichi Matsui, Masamitsu Tanaka, Kyosuke Sano, Akira Fujimaki (Nagoya Univ.), Koki Ishida, Takatsugu Ono, Koji Inoue (Kyushu Univ.) SCE2017-17
Abstract (in Japanese) (See Japanese page) 
(in English) We have started development of high-throughput rapid single-flux-quantum (RSFQ) microprocessors with the aim of higher performance than CMOS microprocessors. The throughput performance was limited in bit-serial processing, which was employed in the RSFQ microprocessors demonstrated so far. We can expect significant improvement in performance independently from word lengths by introducing bit-parallel processing and gate-level-pipelined structure, in which pipeline processing is formed by logic gate. In this study, we aimed to prove the feasibility of bit-parallel RSFQ microprocessors, by evaluating high-frequency operation of datapath, which is the largest, most challenging component in timing design. The high-speed tests of an adder and register file, which compose the datapath, showed bias margins of 25% at the target frequency, 30 GHz. We also designed detailed datapath, and obtained the comparable bias margin at 30 GHz by logic simulation. However, the result revealed the unstable operation at lower bias region, and indicates that we need review of timing design.
Keyword (in Japanese) (See Japanese page) 
(in English) RSFQ circuit / Microprocessor / Gate-level-pipeline / Bit-parallel processing / / / /  
Reference Info. IEICE Tech. Rep., vol. 117, no. 171, SCE2017-17, pp. 37-42, Aug. 2017.
Paper # SCE2017-17 
Date of Issue 2017-08-02 (SCE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SCE2017-17

Conference Information
Committee SCE  
Conference Date 2017-08-09 - 2017-08-10 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagoya Univ. (Higashiyama Campus) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Signal processing technologies and their applications, etc. 
Paper Information
Registration To SCE 
Conference Code 2017-08-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Design of Component Circuits for Rapid Single-Flux-Quantum Gate-Level-Pipelined Microprocessors 
Sub Title (in English)  
Keyword(1) RSFQ circuit  
Keyword(2) Microprocessor  
Keyword(3) Gate-level-pipeline  
Keyword(4) Bit-parallel processing  
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Keyword(6)  
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1st Author's Name Yuki Hatanaka  
1st Author's Affiliation Nagoya University (Nagoya Univ.)
2nd Author's Name Yuichi Matsui  
2nd Author's Affiliation Nagoya University (Nagoya Univ.)
3rd Author's Name Masamitsu Tanaka  
3rd Author's Affiliation Nagoya University (Nagoya Univ.)
4th Author's Name Kyosuke Sano  
4th Author's Affiliation Nagoya University (Nagoya Univ.)
5th Author's Name Akira Fujimaki  
5th Author's Affiliation Nagoya University (Nagoya Univ.)
6th Author's Name Koki Ishida  
6th Author's Affiliation Kyushu University (Kyushu Univ.)
7th Author's Name Takatsugu Ono  
7th Author's Affiliation Kyushu University (Kyushu Univ.)
8th Author's Name Koji Inoue  
8th Author's Affiliation Kyushu University (Kyushu Univ.)
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Speaker Author-1 
Date Time 2017-08-09 14:35:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2017-17 
Volume (vol) vol.117 
Number (no) no.171 
Page pp.37-42 
#Pages 6 
Date of Issue 2017-08-02 (SCE) 

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