IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 118, Number 29

VLSI Design Technologies

Workshop Date : 2018-05-16 / Issue Date : 2018-05-09

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Table of contents

VLD2018-1
Partial logic synthesis by using sum of products or product of sums based quantified boolean formulae
Xiaoran Han, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo)
pp. 1 - 5

VLD2018-2
Non-volatile Power Gating for Data Cache with Dynamic Line-selection
Sosuke Akiba, Kimiyoshi Usami (SIT)
pp. 19 - 24

VLD2018-3
Pixel-based OPC using Quadratic Programming for Mask Optimization
Rina Azuma, Yukihide Kohira (Univ. of Aizu)
pp. 31 - 36

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan