IEICE Technical Report

Online edition: ISSN 2432-6380

Hardware Security

Workshop Date : 2021-04-12 / Issue Date : 2021-04-05

HWS2021-1
Design and Evaluation of High Speed Hardware of Isogeny-based Cryptography Using Residue Number System
Rei Ueno, Naofumi Homma (Tohoku Univ.)
pp. 1 - 6

HWS2021-2
Approximate Solution of Large-Scale Job Shop Scheduling Problem and Its Application to Hardware Cryptographic Design
Kento Ikeda, Makoto Ikeda (Tokyo Univ.)
pp. 7 - 12

HWS2021-3
Performance Evaluation of an FPGA-Based Pairing Computation Accelerator
Junichi Sakamoto, Naoki Yoshida, Tsutomu Matsumoto (YNU)
pp. 13 - 18

HWS2021-4
An Implementation of a Pairing on Cocks-Pinch Curve with Embedding Degree 6
Zihao Song, Junichi Sakamoto, Tsutomu Matsumoto (YNU)
pp. 19 - 24

HWS2021-5
[Invited Talk] Rejection Sampling Schemes for Extracting Uniform Distribution from Biased PUFs (from CHES 2020)
Rei Ueno, Kohei Kazumori, Naofumi Homma (Tohoku Univ.)
p. 25

HWS2021-6
[Invited Talk] PFB: Lightweight Authenticated Encryption Mode of Operation for Tweakable Block Ciphers
Yusuke Naito (Mitsubishi Electric Corp.), Takeshi Sugawara (UEC)
p. 26

HWS2021-7
A division algorithm with constant divisor in the residue number system
Shinichi Kawamura (AIST/Toshiba), Yuichi Komano (Toshiba)
pp. 27 - 32

HWS2021-8
On the Performance Evaluation of Deep-Learning Based Side-Channel Attacks
Akira Ito, Rei Ueno, Naofumi Homma (Tohoku Univ.)
pp. 33 - 38

HWS2021-9
Fundamental Study on Evaluating Frequency Injection Attack Resistance against RO-based TRNGs
Riki Hashimoto, Daisuke Fujimoto, Yuichi Hayashi (NAIST)
pp. 39 - 42

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan