IEICE Technical Report

Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2022-09-07 - 2022-09-08 / Issue Date : 2022-08-31

RECONF2022-26
Efficient Learning of Spiking Neural Networks with Genetic Algorithm and its FPGA Acceleration
Taiki Watanabe, Yukinori Sato (TUT)
pp. 1 - 6

RECONF2022-27
Simulation for a CNN implementation on a multi-FPGA system with system-C description
Shao Ningyu, Hiroaki Suzuki (Keio Univ.), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ.), Hideharu Amano (Keio Univ.)
pp. 7 - 12

RECONF2022-28
(See Japanese page.)
pp. 13 - 14

RECONF2022-29
(See Japanese page.)
pp. 15 - 16

RECONF2022-30
(See Japanese page.)
pp. 17 - 18

RECONF2022-31
(See Japanese page.)
pp. 19 - 20

RECONF2022-32
[Short Paper]
Zuquan Qin, Weu Kaijie, Hideharu Amano (Keio Univ.), Kazuhiro Nakadai (TIT)
pp. 21 - 22

RECONF2022-33
FPGA implementation of small area sum-of-products arithmetic unit for Posit and consideration of its introduction into AI chip ReNA
Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Masahiro Iida (Kumamoto Univ.)
pp. 23 - 28

RECONF2022-34
Proposal and evaluation of Combined Posit MAC unit (CPMAC) for both DNN inference and training
Yuta Masuda, Yasuhiro Nakahara, Masato Kiyama, Masahiro Iida (Kumamoto Univ.)
pp. 29 - 34

RECONF2022-35
(See Japanese page.)
pp. 35 - 40

RECONF2022-36
(See Japanese page.)
pp. 41 - 46

RECONF2022-37
(See Japanese page.)
pp. 47 - 52

RECONF2022-38
(See Japanese page.)
pp. 53 - 56

RECONF2022-39

Takuya Kojima, Kaito Kokubu, Makoto Saito, Yuna Tomida, Shion Maeda (UTokyo)
pp. 57 - 58

RECONF2022-40
(See Japanese page.)
pp. 59 - 60

RECONF2022-41
(See Japanese page.)
pp. 61 - 62

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan