Online edition: ISSN 2432-6380
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RECONF2022-1
Accelerating Deep Learning-based Path Planning Method on FPGAs
Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
pp. 1 - 6
RECONF2022-2
Shoin Maeda, Hiroshi Nakamura, Hideki Takase (UT)
pp. 7 - 12
RECONF2022-3
Hardware implementation of the protocol for ROS2 and robot modules without CPU
Daiki Matsunaga, Tomoya Shoji, Shozo Takeoka (AXE)
pp. 13 - 19
RECONF2022-4
Performance Evaluation of Fault-Tolerant Routing Methods Using NAS Parallel Benchmarks
Yota Kurokawa, Masaru Fukushi (Yamaguchi Univ.)
pp. 20 - 25
RECONF2022-5
Vector Register Sharing Mechanism for Hardware Acceleration
Tomoaki Tanaka, Ryousuke Higashi (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT)
pp. 26 - 31
RECONF2022-6
Optically reconfigurable gate array VLSI with a perfect parallel configuration function
Sae Goto, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 32 - 36
RECONF2022-7
290 Mrad total-ionizing-dose tolerance experiment for an optically reconfigurable gate array VLSI
Kaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 37 - 40
RECONF2022-8
(See Japanese page.)
pp. 41 - 42
RECONF2022-9
An Implementation of a Pattern-matching Accelerator on a RISC-V Processor
Riku Takayama, Jubee Tada (Yamagata Univ.)
pp. 43 - 44
RECONF2022-10
Design of a Quantum Annealing Accelerator for Sparse Ising Model
Yuta Ohma, Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.)
pp. 45 - 47
RECONF2022-11
Preliminary Evaluation of FPGA-to-FPGA Communication Speed in FPGA Cluster ESSPER
Rintaro Sakai, Yasuhiro Nakahara (Kumamoto Univ. /R-CSS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CSS)
pp. 48 - 49
RECONF2022-12
Development of Vehicles GPS Time Synchronized Vibration Measurement System for Bridge Health Monitoring
Masaaki Ono, Ryota Shin, Yukihiko Okada, Ryosuke Yamamoto (Univ. of Tsukuba)
pp. 50 - 51
RECONF2022-13
Investigation of methods to accelerate inference processing by deep learning
Seiya Iwamoto, Chikako Nakanishi (OIT)
pp. 52 - 56
RECONF2022-14
Consideration of speeding up AI inference processing by cooperative operation of hardware and software
Tomoya Kawakami, Chikako Nakanishi (OIT)
pp. 57 - 62
RECONF2022-15
(See Japanese page.)
pp. 63 - 67
RECONF2022-16
(See Japanese page.)
pp. 68 - 73
RECONF2022-17
(See Japanese page.)
pp. 74 - 79
RECONF2022-18
Introduction of Power Monitoring Tool for FPGA Clusters and Power Analysis of FPGA Clusters
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano (Keio Univ)
pp. 80 - 85
RECONF2022-19
(See Japanese page.)
p. 86
RECONF2022-20
Regularization based CNN Optimizing and the acceleration on FPGA
Hengyi Li, Xuebin Yue, Lin Meng (RU)
pp. 87 - 88
RECONF2022-21
A Compact High-Speed CNN Implementation based on Redundant Computational Analysis and FPGA Acceleration
Li Qi, Li Hengyi, Meng Lin (Ritsumeikan Univ.)
pp. 89 - 94
RECONF2022-22
Structural Sparsification of Activations and Weights for Low Latency Implementation of CNN
Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech)
pp. 95 - 100
RECONF2022-23
A Parallel Processing of Point Feature Histogram on FPGAs
Ryuto Kojima, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
pp. 101 - 106
RECONF2022-24
(See Japanese page.)
pp. 107 - 112
RECONF2022-25
(See Japanese page.)
pp. 113 - 118
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.