Online edition: ISSN 2432-6380
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RECONF2023-19
Monitoring system for optically reconfigurable gate arrays under radiation environments
Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 1 - 5
RECONF2023-20
Implementation of a sequential circuit onto an optically reconfigurable gate array VLSI without any crystal oscillator
Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 6 - 10
RECONF2023-21
Building Simulation Environment for Reconfigurable Virtual Accelerator (ReVA)
Shunya Kawai, Kazuki Yaguchi, Eriko Maeda (TUAT), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT)
pp. 11 - 12
RECONF2023-22
Integrating RISC-V Vector Extension and SMT for Embedded AI Workloads
Hidetaro Tanaka, Shogo Takata, Hironori Nakajo (TUAT)
pp. 13 - 14
RECONF2023-23
(See Japanese page.)
pp. 15 - 17
RECONF2023-24
Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism
Go Akamatsu, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT)
pp. 18 - 19
RECONF2023-25
Construction of Visualization Environment for CGRA Operation Verification
Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura (UT)
pp. 20 - 21
RECONF2023-26
(See Japanese page.)
pp. 22 - 27
RECONF2023-27
SATA burst data transfer pattern of state vector simulator
Hideharu Amano, Wei Kaijie (Keio Univ.), Ryohei Nisawa (Univ. of Tsukuba), Takefumi Miyoshi (Wasalabo), Yoshiki Yamaguchi (Univ. of Tsukuba)
pp. 28 - 33
RECONF2023-28
*
Shintaro Kawasaki, Mizuki Ito, Yoshiki Yamaguchi ()
pp. 34 - 39
RECONF2023-29
Implementation and Evaluation of a Hardware Accelerator via Vector Register Sharing Mechanism for Massive Data Transfer
Michiya Kato, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi MIyoshi (Wasarabo LLC), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT)
pp. 40 - 45
RECONF2023-30
Abstraction of Processor-FPGA Communication in Reconfigurable Virtual Accelerator (ReVA)
Eriko Maeda, Kazuki Yaguchi, Shunya Kawai, Daichi Teruya (TUAT), Yasunori Osana (Kumamoto Univ.), Takehumi Miyoshi (Wasalabo), Hironori Nakajo (TUAT)
pp. 46 - 51
RECONF2023-31
Library Development for RISC-V FPGA SoCs
Takuya Kojima (UTokyo/JST PRESTO), Yosuke Yanai (Keio Univ.), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.)
pp. 52 - 57
RECONF2023-32
On the FPGA Implementation of a Lightweight Neural Network for Point Clouds
Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
pp. 58 - 63
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.