| Paper Abstract and Keywords |
| Presentation |
2005-09-16 09:00
Programmable Numerical Function Generators: Architectures and Synthesis Method
Shinobu Nagayama (Hiroshima City Univ.), Tsutomu Sasao (K.I.T), Jon T. Butler (Naval Postgraduate School) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This paper presents an architecture and a synthesis method for programmable numerical function generators (NFGs) of trigonometric functions, logarithm functions, square root, reciprocal, etc. Our architecture partitions a given domain of function into non-uniform segments using an LUT (Look-Up Table) cascade, and approximates the given function by a linear polynomail for each segment. Thus, our architecture can implement fast and compact NFGs for a wide range of functions. We have developed a synthesis system for NFGs that converts MATLAB-like specification into HDL code. We show and compare three architectures implemented as a FPGA (Field-Programmable Gate Array). Experimental results show the efficiency of our architecture and synthesis system. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
LUT cascades / numerical function generators / pipeline processing / automatic synthesis / FPGA / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 105, no. 288, RECONF2005-41, pp. 1-6, Sept. 2005. |
| Paper # |
RECONF2005-41 |
| Date of Issue |
2005-09-09 (RECONF) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
RECONF |
| Conference Date |
2005-09-15 - 2005-09-16 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
|
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Reconfigurable Systems, etc. |
| Paper Information |
| Registration To |
RECONF |
| Conference Code |
2005-09-RECONF |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Programmable Numerical Function Generators: Architectures and Synthesis Method |
| Sub Title (in English) |
|
| Keyword(1) |
LUT cascades |
| Keyword(2) |
numerical function generators |
| Keyword(3) |
pipeline processing |
| Keyword(4) |
automatic synthesis |
| Keyword(5) |
FPGA |
| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Shinobu Nagayama |
| 1st Author's Affiliation |
Hiroshima City University (Hiroshima City Univ.) |
| 2nd Author's Name |
Tsutomu Sasao |
| 2nd Author's Affiliation |
Kyushu Institute of Technology (K.I.T) |
| 3rd Author's Name |
Jon T. Butler |
| 3rd Author's Affiliation |
Naval Postgraduate School (Naval Postgraduate School) |
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| Speaker |
Author-1 |
| Date Time |
2005-09-16 09:00:00 |
| Presentation Time |
30 minutes |
| Registration for |
RECONF |
| Paper # |
RECONF2005-41 |
| Volume (vol) |
vol.105 |
| Number (no) |
no.288 |
| Page |
pp.1-6 |
| #Pages |
6 |
| Date of Issue |
2005-09-09 (RECONF) |