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Paper Abstract and Keywords
Presentation 2005-10-21 10:30
Single-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors
Atsushi Tanaka, Atsuhiro Suga, Fumihiko Hayakawa, Shinichiro Tago, Satoshi Imai (Fujitsu Lab) Link to ES Tech. Rep. Archives: ICD2005-138
Abstract (in Japanese) (See Japanese page) 
(in English) To realize the low power consumption and low-cost equipment needed to encode high-definition broadcasts, we have developed a FR1000 single-chip multicore processor that integrates four 8-way VLIW FR-V processor cores. This new multicore processor cores operate at 533 MHz, the memory interfaces at 266 MHz, and the system bus at 178 MHz. By using four processor cores, MPEG2 MP@HL video streams can be decoded using just software. This processor needs three watts to decode MPEG2 MP@HL video streams.
Keyword (in Japanese) (See Japanese page) 
(in English) embedded / microprocessor / chip multi-processor / multi-core processor / low-power / / /  
Reference Info. IEICE Tech. Rep., vol. 105, no. 352, ICD2005-138, pp. 25-29, Oct. 2005.
Paper # ICD2005-138 
Date of Issue 2005-10-14 (SIP, ICD, IE) 
ISSN Print edition: ISSN 0913-5685  Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF Link to ES Tech. Rep. Archives: ICD2005-138

Conference Information
Committee SIP ICD IE IPSJ-SLDM  
Conference Date 2005-10-20 - 2005-10-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Ichinobo, Sakunami-Spa 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Processor, DSP, Image Engineering and etc. 
Paper Information
Registration To ICD 
Conference Code 2005-10-SIP-ICD-IE-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Single-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors 
Sub Title (in English)  
Keyword(1) embedded  
Keyword(2) microprocessor  
Keyword(3) chip multi-processor  
Keyword(4) multi-core processor  
Keyword(5) low-power  
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1st Author's Name Atsushi Tanaka  
1st Author's Affiliation Fujitsu Laboratories (Fujitsu Lab)
2nd Author's Name Atsuhiro Suga  
2nd Author's Affiliation Fujitsu Laboratories (Fujitsu Lab)
3rd Author's Name Fumihiko Hayakawa  
3rd Author's Affiliation Fujitsu Laboratories (Fujitsu Lab)
4th Author's Name Shinichiro Tago  
4th Author's Affiliation Fujitsu Laboratories (Fujitsu Lab)
5th Author's Name Satoshi Imai  
5th Author's Affiliation Fujitsu Laboratories (Fujitsu Lab)
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Speaker
Date Time 2005-10-21 10:30:00 
Presentation Time 20 
Registration for ICD 
Paper # SIP2005-119, ICD2005-138, IE2005-83 
Volume (vol) 105 
Number (no) no.350(SIP), no.352(ICD), no.354(IE) 
Page pp.25-29 
#Pages
Date of Issue 2005-10-14 (SIP, ICD, IE) 


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