| Paper Abstract and Keywords |
| Presentation |
2006-05-12 14:00
Measurement and Analysis of Delay and Power Variations in 90nm CMOS Circuits Masaki Yamaguchi (Kyushu Univ.), Yang Yuan (Xi'an Univ. of Technology), Kosuke Tarumi, Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
As the transistor size shrinks, process variations increase. Under the existence of the variations, an existing design flow will not be effective for minimizing the worst-case circuit delay and average power consumption. As the first step toward developing a better solution, this paper investigates basic characteristics of the delay and the power variation. We measured delay and power consumption values for 1,890 ring oscillator circuits designed with 90nm CMOS technology. We also analyzed both intra-chip and inter-chip variations for delay, dynamic power consumption and leakage power consumption. The measurement results demonstrated that the leakage power variation is very large and the inter-chip variations are larger than the intra-chip variations. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
delay variation / power variation / Deep Sub-Micron / CMOS / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 106, no. 32, VLD2006-13, pp. 41-46, May 2006. |
| Paper # |
VLD2006-13 |
| Date of Issue |
2006-05-05 (VLD) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
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| Conference Information |
| Committee |
VLD IPSJ-SLDM |
| Conference Date |
2006-05-11 - 2006-05-12 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Ehime University |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
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| Paper Information |
| Registration To |
VLD |
| Conference Code |
2006-05-VLD-IPSJ-SLDM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Measurement and Analysis of Delay and Power Variations in 90nm CMOS Circuits |
| Sub Title (in English) |
|
| Keyword(1) |
delay variation |
| Keyword(2) |
power variation |
| Keyword(3) |
Deep Sub-Micron |
| Keyword(4) |
CMOS |
| Keyword(5) |
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| Keyword(6) |
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| Keyword(8) |
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| 1st Author's Name |
Masaki Yamaguchi |
| 1st Author's Affiliation |
Kyushu University (Kyushu Univ.) |
| 2nd Author's Name |
Yang Yuan |
| 2nd Author's Affiliation |
Xi'an University of Technology (Xi'an Univ. of Technology) |
| 3rd Author's Name |
Kosuke Tarumi |
| 3rd Author's Affiliation |
Kyushu University (Kyushu Univ.) |
| 4th Author's Name |
Ryota Sakamoto |
| 4th Author's Affiliation |
Kyushu University (Kyushu Univ.) |
| 5th Author's Name |
Masanori Muroyama |
| 5th Author's Affiliation |
Kyushu University (Kyushu Univ.) |
| 6th Author's Name |
Tohru Ishihara |
| 6th Author's Affiliation |
Kyushu University (Kyushu Univ.) |
| 7th Author's Name |
Hiroto Yasuura |
| 7th Author's Affiliation |
Kyushu University (Kyushu Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2006-05-12 14:00:00 |
| Presentation Time |
30 minutes |
| Registration for |
VLD |
| Paper # |
VLD2006-13 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.32 |
| Page |
pp.41-46 |
| #Pages |
6 |
| Date of Issue |
2006-05-05 (VLD) |