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| Presentation | 2007-01-18 10:15 Measurement of Delay Degradation Due to Power Supply Noise and Delay Variation Estimation with Full-Chip Simulation Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto (Osaka Univ.), Takashi Sato (Tokyo Inst. Tech.), Takao Onoye (Osaka Univ.) Link to ES Tech. Rep. Archives:  CPM2006-132 ICD2006-174 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Power integrity is an crucial design issue in nano-meter technologies because of lowered supply voltage and current increase. This paper focuses on gate delay variation due to power/ground noise, and demonstrates measurement results in a 90nm technology. For full-chip simulation, a current model with capacitance and variable resistor is developed to accurately model current dependency on voltage drop. Measurement results are well correlated with simulation, and verify that gate delay depends on average voltage drop. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | power supply noise / full-chip simulation / transistor model / delay estimation / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 106, no. 468, ICD2006-174, pp. 19-23, Jan. 2007. | |
| Paper # | ICD2006-174 | |
| Date of Issue | 2007-01-11 (CPM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: CPM2006-132 ICD2006-174 |
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| Conference Information | |
| Committee | ICD CPM |
| Conference Date | 2007-01-18 - 2007-01-19 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kika-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | LSI system assembly and module/inteface technology, test, general |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-01-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Measurement of Delay Degradation Due to Power Supply Noise and Delay Variation Estimation with Full-Chip Simulation |
| Sub Title (in English) | |
| Keyword(1) | power supply noise |
| Keyword(2) | full-chip simulation |
| Keyword(3) | transistor model |
| Keyword(4) | delay estimation |
| Keyword(5) | |
| Keyword(6) | |
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| Keyword(8) | |
| 1st Author's Name | Yasuhiro Ogasahara |
| 1st Author's Affiliation | Osaka University (Osaka Univ.) |
| 2nd Author's Name | Takashi Enami |
| 2nd Author's Affiliation | Osaka University (Osaka Univ.) |
| 3rd Author's Name | Masanori Hashimoto |
| 3rd Author's Affiliation | Osaka University (Osaka Univ.) |
| 4th Author's Name | Takashi Sato |
| 4th Author's Affiliation | Tokyo Institute of Technology (Tokyo Inst. Tech.) |
| 5th Author's Name | Takao Onoye |
| 5th Author's Affiliation | Osaka University (Osaka Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-01-18 10:15:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | CPM2006-132, ICD2006-174 |
| Volume (vol) | vol.106 |
| Number (no) | no.467(CPM), no.468(ICD) |
| Page | pp.19-23 |
| #Pages | 5 |
| Date of Issue | 2007-01-11 (CPM, ICD) |
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