| Paper Abstract and Keywords |
| Presentation |
2007-01-26 10:55
Design and Implementation of Bit-Slice Adder
Heejoung Park, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.), Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.), Hirotaka Terai (NICT), Shinichi Yorozu (NEC) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Recently, a lot of researches on designing digital circuits by using SFQ logic circuits have been carried out extensively. We have been developing SFQ microprocessors based on the CORE architecture. In our SFQ microprocessor design, a bit-serial architecture, where the width of the data processed at the same time is 1-bit, has been used up to now to simplify the hardware complexity. In order to increase the performance of the microprocessor, however, we have to increase the width of the data processed at the same time, i.e. bit-slice width. In this paper, we present an architecture of bit-slice adder. In the proposed bit-slice adder, a logarithmic carry look-ahead adder architecture (CLA) was adapted to generate the carries, where the carries generated in the bit-slice data are fed back into the following bit-slice data internally to increase the throughput of the operation. We will show dependences of the operating time and the hardware cost of the bit-slice adder on the bit-slice width. We have also implemented a 4b bit-slice adder using SRL 2.5 kA/cm^2 niobium standard process, and demonstrated its high-speed operation. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
SFQ logic circuit / bit-slice adder / adder / CORE architecture / carry look-ahead adder / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 106, no. 503, SCE2006-32, pp. 13-18, Jan. 2007. |
| Paper # |
SCE2006-32 |
| Date of Issue |
2007-01-19 (SCE) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
SCE |
| Conference Date |
2007-01-26 - 2007-01-26 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
SRL |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Digital electronics, etc |
| Paper Information |
| Registration To |
SCE |
| Conference Code |
2007-01-SCE |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Design and Implementation of Bit-Slice Adder |
| Sub Title (in English) |
|
| Keyword(1) |
SFQ logic circuit |
| Keyword(2) |
bit-slice adder |
| Keyword(3) |
adder |
| Keyword(4) |
CORE architecture |
| Keyword(5) |
carry look-ahead adder |
| Keyword(6) |
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| Keyword(7) |
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| 1st Author's Name |
Heejoung Park |
| 1st Author's Affiliation |
Yokohama National University (Yokohama National Univ.) |
| 2nd Author's Name |
Yuki Yamanashi |
| 2nd Author's Affiliation |
Yokohama National University (Yokohama National Univ.) |
| 3rd Author's Name |
Nobuyuki Yoshikawa |
| 3rd Author's Affiliation |
Yokohama National University (Yokohama National Univ.) |
| 4th Author's Name |
Masamitsu Tanaka |
| 4th Author's Affiliation |
Nagoya University (Nagoya Univ.) |
| 5th Author's Name |
Akira Fujimaki |
| 5th Author's Affiliation |
Nagoya University (Nagoya Univ.) |
| 6th Author's Name |
Hirotaka Terai |
| 6th Author's Affiliation |
National Institute of Information and Communications Technology (NICT) |
| 7th Author's Name |
Shinichi Yorozu |
| 7th Author's Affiliation |
NEC (NEC) |
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| Speaker |
Author-1 |
| Date Time |
2007-01-26 10:55:00 |
| Presentation Time |
25 minutes |
| Registration for |
SCE |
| Paper # |
SCE2006-32 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.503 |
| Page |
pp.13-18 |
| #Pages |
6 |
| Date of Issue |
2007-01-19 (SCE) |