| Paper Abstract and Keywords |
| Presentation |
2007-03-07 17:40
A Study of Dependence on Gate Depth/Width for Analyzing Delay/Power Variations in 90nm CMOS Circuits
Masaki Yamaguchi (Kyushu Univ.), Yuan Yang (Xi’an Univ. of Technology), Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
As the transistor size shrinks, process variations increase. Under the existence of the variations, an existing design flow will not be effective for minimizing the worst-case circuit delay and average power consumption. As the first step toward developing a better solution, this paper investigates basic characteristics of the delay/power variation.
We measured delay/power consumption values for 5 kinds of ring oscillator circuits with some gate depth/width designed with 90nm CMOS technology. We analyzed delay/power variations dependence on gate Depth/width. The measurement results demonstrated that delay variations can be suppressed by increasing the number of gate steps and showed that delay/power variations increase by enlarging gate width. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Delay Variation / Power Variation / CMOS / Deep Sub-Micron / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 106, no. 550, ICD2006-209, pp. 73-78, March 2007. |
| Paper # |
ICD2006-209 |
| Date of Issue |
2007-02-28 (VLD, ICD) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
ICD VLD |
| Conference Date |
2007-03-07 - 2007-03-09 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Mielparque Okinawa |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
System-on-silicon design techniques and related VLSs |
| Paper Information |
| Registration To |
ICD |
| Conference Code |
2007-03-ICD-VLD |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
A Study of Dependence on Gate Depth/Width for Analyzing Delay/Power Variations in 90nm CMOS Circuits |
| Sub Title (in English) |
|
| Keyword(1) |
Delay Variation |
| Keyword(2) |
Power Variation |
| Keyword(3) |
CMOS |
| Keyword(4) |
Deep Sub-Micron |
| Keyword(5) |
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| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Masaki Yamaguchi |
| 1st Author's Affiliation |
Kyushu University (Kyushu Univ.) |
| 2nd Author's Name |
Yuan Yang |
| 2nd Author's Affiliation |
Xi’an University of Technology (Xi’an Univ. of Technology) |
| 3rd Author's Name |
Ryota Sakamoto |
| 3rd Author's Affiliation |
Kyushu University (Kyushu Univ.) |
| 4th Author's Name |
Masanori Muroyama |
| 4th Author's Affiliation |
Kyushu University (Kyushu Univ.) |
| 5th Author's Name |
Tohru Ishihara |
| 5th Author's Affiliation |
Kyushu University (Kyushu Univ.) |
| 6th Author's Name |
Hiroto Yasuura |
| 6th Author's Affiliation |
Kyushu University (Kyushu Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2007-03-07 17:40:00 |
| Presentation Time |
20 minutes |
| Registration for |
ICD |
| Paper # |
VLD2006-118, ICD2006-209 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.547(VLD), no.550(ICD) |
| Page |
pp.73-78 |
| #Pages |
6 |
| Date of Issue |
2007-02-28 (VLD, ICD) |