Paper Abstract and Keywords |
Presentation |
2007-03-08 15:10
A CAM Emulator Using Look-Up Table Cascades Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.) Link to ES Tech. Rep. Archives: ICD2006-225 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
An address table relates k different registered vectors to the addresses from 1 to k.
An address generation function represents the address table.
This paper presents a realization of an address generation function with an LUT cascade
on an FPGA.
The address generation function is implemented by BRAMs of an FPGA,
while the addition and the deletion of registered vectors are implemented by
an embedded processor on the FPGA.
Compared with CAMs produced by the Xilinx Core Generator,
our implementations are smaller and faster.
This paper also shows that the addition and deletion of a registered vector
can be done in a time that is proportional to the number of cells in the LUT cascade. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
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Reference Info. |
IEICE Tech. Rep., vol. 106, no. 548, VLD2006-134, pp. 91-96, March 2007. |
Paper # |
VLD2006-134 |
Date of Issue |
2007-03-01 (VLD, ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
Link to ES Tech. Rep. Archives: ICD2006-225 |
Conference Information |
Committee |
ICD VLD |
Conference Date |
2007-03-07 - 2007-03-09 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Mielparque Okinawa |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System-on-silicon design techniques and related VLSs |
Paper Information |
Registration To |
VLD |
Conference Code |
2007-03-ICD-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
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(See Japanese page) |
Title (in English) |
A CAM Emulator Using Look-Up Table Cascades |
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1st Author's Name |
Hiroki Nakahara |
1st Author's Affiliation |
Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
2nd Author's Name |
Tsutomu Sasao |
2nd Author's Affiliation |
Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
3rd Author's Name |
Munehiro Matsuura |
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Kyushu Institute of Technology (Kyushu Inst. of Tech.) |
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Speaker |
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Date Time |
2007-03-08 15:10:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
VLD2006-134, ICD2006-225 |
Volume (vol) |
vol.106 |
Number (no) |
no.548(VLD), no.551(ICD) |
Page |
pp.91-96 |
#Pages |
6 |
Date of Issue |
2007-03-01 (VLD, ICD) |
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