| Paper Abstract and Keywords |
| Presentation |
2007-03-08 09:10
SIMD Instructions Generation Algorithm for Multiple Loop for SIMD Processor Cores Optimum Design
Hiroki Nakajima, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
The hardware/software cosynthesis system named SPADES which synthesize a processor with packed SIMD type instructions needs a parallelizing compiler for the processor with packked SIMD type instructions.
The parallelizing compiler targets the virtual processor that has all available hardware units. It exploits instruction level
parallelism using packked SIMD type instructions and output fastest scheduled assembly codes. The output of the parallelizimg compiler
decides the initial configuration of the processor. This paper proposes a parallelizing algrithm for multi loop and a
packed SIMD instruction generation algorithm.
The proposed algorithm extracts instruction level parallelism from multi loop in input application and enables to
generate packed SIMD type instructions.
Experimental results show effectiveness of the proposed algorithm. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
hardware/software cosynthesis / packed SIMD type instructions / compiler / embedded processor / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 106, no. 548, VLD2006-121, pp. 13-18, March 2007. |
| Paper # |
VLD2006-121 |
| Date of Issue |
2007-03-01 (VLD, ICD) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
ICD VLD |
| Conference Date |
2007-03-07 - 2007-03-09 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Mielparque Okinawa |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
System-on-silicon design techniques and related VLSs |
| Paper Information |
| Registration To |
VLD |
| Conference Code |
2007-03-ICD-VLD |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
SIMD Instructions Generation Algorithm for Multiple Loop for SIMD Processor Cores Optimum Design |
| Sub Title (in English) |
|
| Keyword(1) |
hardware/software cosynthesis |
| Keyword(2) |
packed SIMD type instructions |
| Keyword(3) |
compiler |
| Keyword(4) |
embedded processor |
| Keyword(5) |
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| Keyword(6) |
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| Keyword(7) |
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| 1st Author's Name |
Hiroki Nakajima |
| 1st Author's Affiliation |
Waseda University (Waseda Univ.) |
| 2nd Author's Name |
Shunitsu Kohara |
| 2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
| 3rd Author's Name |
Nozomu Togawa |
| 3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
| 4th Author's Name |
Masao Yanagisawa |
| 4th Author's Affiliation |
Waseda University (Waseda Univ.) |
| 5th Author's Name |
Tatsuo Ohtsuki |
| 5th Author's Affiliation |
Waseda University (Waseda Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2007-03-08 09:10:00 |
| Presentation Time |
20 minutes |
| Registration for |
VLD |
| Paper # |
VLD2006-121, ICD2006-212 |
| Volume (vol) |
vol.106 |
| Number (no) |
no.548(VLD), no.551(ICD) |
| Page |
pp.13-18 |
| #Pages |
6 |
| Date of Issue |
2007-03-01 (VLD, ICD) |