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| Presentation | 2007-04-12 09:00 MRAM Cell Technology for High-speed SoCs Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Kenichi Shimura, Naoki Kasai (NEC)  ICD2007-1 Link to ES Tech. Rep. Archives: ICD2007-1 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We has succeeded in developing new MRAM cell technology suitable for high-speed memory macro embedded in next generation system LSIs. The new cell technology includes three key elements; a 2T1MTJ cell structure to accelerate write mode cycle time, a 5T2MTJ cell structure to accelerate read mode cycle time and a write-line-inserted MTJ to reduce writing current. It realized added-value, non-volatile MRAM macros that can be substituted for SRAM macros embedded in system LSIs operating at over 200MHz. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | MRAM / Embedded Memories / System LSIs / High-speed / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 1, ICD2007-1, pp. 1-5, April 2007. | |
| Paper # | ICD2007-1 | |
| Date of Issue | 2007-04-05 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2007-1 Link to ES Tech. Rep. Archives: ICD2007-1 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2007-04-12 - 2007-04-13 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-04-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | MRAM Cell Technology for High-speed SoCs |
| Sub Title (in English) | |
| Keyword(1) | MRAM |
| Keyword(2) | Embedded Memories |
| Keyword(3) | System LSIs |
| Keyword(4) | High-speed |
| Keyword(5) | |
| Keyword(6) | |
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| Keyword(8) | |
| 1st Author's Name | Noboru Sakimura |
| 1st Author's Affiliation | NEC Corporation (NEC) |
| 2nd Author's Name | Tadahiko Sugibayashi |
| 2nd Author's Affiliation | NEC Corporation (NEC) |
| 3rd Author's Name | Ryusuke Nebashi |
| 3rd Author's Affiliation | NEC Corporation (NEC) |
| 4th Author's Name | Hiroaki Honjo |
| 4th Author's Affiliation | NEC Corporation (NEC) |
| 5th Author's Name | Kenichi Shimura |
| 5th Author's Affiliation | NEC Corporation (NEC) |
| 6th Author's Name | Naoki Kasai |
| 6th Author's Affiliation | NEC Corporation (NEC) |
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| Speaker | Author-1 |
| Date Time | 2007-04-12 09:00:00 |
| Presentation Time | 30 minutes |
| Registration for | ICD |
| Paper # | ICD2007-1 |
| Volume (vol) | vol.107 |
| Number (no) | no.1 |
| Page | pp.1-5 |
| #Pages | 5 |
| Date of Issue | 2007-04-05 (ICD) |
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